搜索资源列表
相位差可调的双通道信号发生器的设计
- 相位差可调的双通道信号发生器的设计,可以作为信号源用-phase difference adjustable dual-channel signal generator, we can use as a signal source
usb_HLD3Core(400)_(B)
- 接ADDA 板卡，外接信号源（峰峰值最大为1V），运行PC 端程序可 以将输入的信号源波形在PC 上显示出来，完成USB 的数据采集功能。-access ADDA Card, external signal source (peak to peak largest 1V), PC-operating procedures can be the source of the input signal waveform displayed on the PC, and complete USB d
dds_fpga
- DDS在现在运用月来越广泛，在相对带宽、频率转换时间、相位连续性、正交输出、高分辨力以及集成化等方面都远远超过了传统频率合成技术所能达到的水平，为系统提供了优于模拟信号源的性能。利用DDS技术可以很方便地实现多种信号。在FPGA上实现的DDS-DDS now to the use of more extensive relative bandwidth, frequency conversion time, phase continuity, quadrature output, high-re
CCDOUT
- CCD信号由于其特殊性,一般不能有信号源产生,本程序采用VHDL语言，以ISE为开发平台，产生了模拟CCD信号的数字信号，只需经DA转换便能实现-CCD signal because of its uniqueness, not generally produce a signal source, the procedures used VHDL, ISE as a development platform, have CCD signal simulation of digital signa
dds
- 基于飓风1 fpga 和stc单片机的dds信号源 程序是自己些的 能用 最大频率是2M
VHDLannunciator
- 用VHDL语言写的DDS信号源，有源码，非常详细，很有综合性
DDS_信号源
- dds 精确步进100HZ.拨码开关选择FSK,FM等功能.最高频率25M,DA芯片9760.VHDL编写
b_pro3_restored
- 2011年电子设计大赛e题《简易数字信号传输分析仪》verilog源代码，分信号源和分析仪两部分-2011 electronic design competition e question the simple digital signal transfers analyzer "verilog the source code, and the points the signal source and the two parts analyzer
DDS-STC89C52-DAC0800-FPGA.doc
- 电子设计大赛，波形发生器，基于单片机和FPGA的DDS信号源。-Electronic Design Contest, waveform generator, microcontroller and FPGA-based DDS signal source.
singnal
- VHDL实现通用通信信号源，包括sin，cos，方波，三角波，BPSK，GMSK，ASK，16QAM等信号的产生以及DDS，PLL的VHDL系统代码-VHDL implementation of universal communication sources, including sin, cos, square, triangle, BPSK, GMSK, ASK, 16QAM and other signal generation and DDS, PLL system, the VHDL
QuartusIIVHDLDDS
- 基于FPGA的DDS信号源设计全部内容，可以输出显示频率-FPGA-based design of the DDS signal source of all content, you can display the output frequency
Nios_II_SOPC
- 基于Nios＿II软核处理器的通信信号源SOPC设计，很有用的资料．-Nios_II soft-core processor-based communication signal source SOPC design, very useful information.
dds
- dds算法的fpga实现 altera 根据不同设置，输出不同频率的信号源-dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies
cossin
- 数字信号源，输出不同频率，相位的正余弦信号，-Digital signal source, the output of different frequency, phase is the cosine signal,
logicFPGA
- 电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)-Electronic Design Competition works _ audio signal source analyzer FPGA (first prize)
sanxiangxinhaoyuan
- 基于vhdl的三相信号源，可任意置频率和相位，还有调频输出模式，可以输出调频波-Vhdl-based three-phase signal source can be arbitrary frequency and phase of home, as well as frequency modulation output mode, you can output FM wave
sanxiangxinhaoyuan_c_yuyan
- 三相信号源与fpga通讯的程序，控制写频率和相位控制字-Three-phase source fpga communications and procedures to control the frequency and phase control to write the word
FSK_FPGA
- FSK模拟信号源，利用ISE7.1或以上环境打开。-FSK signal simulator.The project can be open in ISE7.1 or upgrade version.
dds_9760_OK
- ＤＤＳ信号源程序，用ＶＨＤＬ编的。里面可用拨码开关选择相应的功能：ＦＭ，ＡＳＫ，ＰＳＫ，ＡＭ（这一点实现的不是很好），但其它的很好。频率可达２５Ｍ-DDS signal source, for the use of VHDL. DIP switch which can be used to select the appropriate function: FM, ASK, PSK, AM (This is not to achieve good), but other well. Frequen
数字信号处理的FPGA实现(第4版)源码
- 数字信号处理的FPGA实现(第4版)的配套源码，极具参考价值。(The source code of the realization of digital signal processing on FPGA (4th edition) is of great reference value.)