搜索资源列表
adder.rar
- 一位全加器可由两个一位半加器与一个或门构成，该设计利用层次结构描述法，首先设计半加器电路，将其打包为半加器模块；然后在顶层调用半加器模块组成全加器电路,A full adder can be two a half-adder and an OR gate structure, the design is the use of hierarchical descr iption method, first of all the design half-adder circuit, be packa
sdram_ver_134
- SDRAM控制器的源代码打包下载，不错不错值得-SDRAM controller source code pack download, well worth a good try
laboratory-10
- 基于DE2开发板的实例10进行编写，为整个工程的打包文件-this is a file for lab10 of DE2,you can use this to learn how to design a processor
XILINX_ML505_REVA_ASSY_110306
- XILINX公司的ML505开发板参考设计源码打包-XILINX
watchver
- 一个VHDL编写的时钟的程序，全部源代码打包上传-The clock to prepare a VHDL process, all source code packaged Upload
machester_VHDL
- manchester码在通信领域中用途广泛 这个VHDL程序包括曼彻斯特码的打包和解包。。很难得哦-manchester code in the communications area of a wide range of uses of this process includes the VHDL code packaged Manchester reconciliation package. . Oh, a rare
Windy_VGA_1c6
- 在cyclone EP1C6 上实现VGA 1028*768 16M色的显卡显示功能，而且还做了一个8色的VGA接口，可以实现双头输出。完整的QuartusII 工程，我也把相关的图片一起打包了。本人是作者，看不懂可联系：13802939662-In the cyclone EP1C6 achieve VGA 1028* 768 16M color graphics display, but also made an 8-color VGA interface, dual-head output
clock
- 这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clo
DDS_verilog
- 通讯中常用的dds模块的verilog源码打包下载-Communications commonly used in dds module verilog source code package to download
seg7_controller
- 七段译码器循环显示，并打包为IP核，可在其他程序中使用，已调试，可用。-Seven segment display decoder loop, and packaged as IP cores, can be used in other programs have debugging available.
leddisplay
- microblaze打包文件，功能是在led上显示的管脚说明-microblaze packaged file
fulladder
- 由数字电路知识可知，一位全加器可由两个一位半加器与一个或门构成，其原理图如图1所示。该设计利用层次结构描述法，首先设计半加器电路，将其打包为半加器模块；然后在顶层调用半加器模块组成全加器电路；最后将全加器电路编译下载到实验箱，其中ain,bin,cin信号可采用实验箱上SW0,SW1,SW2键作为输入，并将输入的信号连接到红色LED管LEDR0,LEDR1,LEDR2上便于观察，sum,cout信号采用绿色发光二极管LEDG0,LEDG1来显示。 图1.1 全加器原理图-it s a
verilog
- verialog 编码语言资料，打包下载
led_seq_demo
- 跑马灯的打包verilog程序，包括v和ucf,以及能直接下载的xise文件-The Marquee verilog program package, including v and ucf, and can be downloaded directly xise file
clock
- 闹钟 运用quartus2软件编写程序，具有调整时间，设置闹钟，整点报时等功能，将整个工程打包了-Alarm Clock using quartus2 software programming, adjust the time, set the alarm, the whole point timekeeping function, the whole project package
VHDL
- 数字电路实验程序代码打包下载 版本 宁波大学学年数字电路实验 VHDl编程 部分 -Digital circuit experiment program code package download version Ningbo University academic year programming section VHDl digital circuit experiment
Project-verilog-taxi
- 纯verilog语言编写实现了出租车计费系统的打包好的quartus ii工程。-Pure verilog language to achieve a good package quartus ii engineering taxi billing system.
Four-binary-adder
- 熟悉 VHDL 语言的模块化设计，了解元件例化和打包调用语句。用 VHDL 语言设计一半加器电路，然后用元件例化（COMPONENT）语句调用两个半加器电路，用结构描述实现一个全加器。-The modular design of VHDL language familiar to understand the components and packing cases call statement. Design using VHDL half-adder circuit, and then us
key_alone
- 4x4矩阵键盘扫描 去抖动 带编码输出 模块打包-the program of key scan
pal_disp
- 实现模拟PAL格式数据，并打包成BT656到监视器显示，过程中完成了PAL打包BT656，乒乓操作、监视器配置控制等-PAL to BT656 package, monitor control