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基于VHDL 的数字时钟
- 用VHDL实现时钟的显示，包括七段数码管和lcd1602字符液晶，可以显示十分秒，年月日
vgaclock.rar
- vga显示的数字时钟,用mif文件实现，用以大家学习交流,vga display digital clock, with the realization of mif file for them to learn from the exchange of
vhdl
- 基于vhdl的数字时钟；24制，带有定时，闹钟等功能。-VHDL-based digital clock 24 system, with time, alarm clock functions.
digitalclockvhdl
- EAD设计VHDL语言环境数字时钟数码管显示方案，包括时间设置、调整等。-VHDL language environment EAD design digital digital clock display, including time for setup, adjustment.
myled4
- 四位动态数码管显示数字时钟的分位和秒位。工具：Quartus ii 6.0 语言：VHDL-4 shows the number of dynamic digital tube digital clock and seconds bit. Tools: Quartus ii 6.0 Language: VHDL
verilog
- 多功能数字时钟的verilog语言描述，基于quarters II平台-Multifunction digital clock verilog language descr iption of quarters II-based platforms
clock
- 这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clo
eetop.cn_digital_clock
- 基于VHDL的数字时钟设计课件，简单，实用-VHDL-based Digital Clock Design Courseware
shuzishizhong
- 用verilog语言写的数字时钟程序 芯片是EP2C8Q208C8-Verilog language used to write the digital clock program chip EP2C8Q208C8
Digitalclock_vhdl
- VHDL语言编写的数字时钟代码，环境quartus-Digital clock written in VHDL code, the environment quartusII
shuzishizhong
- 本实验实现一个能显示小时，分钟，秒的数字时钟。数字时钟-The experimental realization of a can display hours, minutes, seconds, the digital clock. Digital Clock
clock
- 基于VHDL硬件描述语言设计的多功能数字时钟的思路和技巧-VHDL hardware descr iption language based on multi-functional digital clock design ideas and techniques
Digital-clock-circuit-diagram
- 数字钟的电路图.1.显示时、分、秒。2. 可以24小时制或12小时制。3. 具有校时功能，可以对小时和分单独校时，对分校时的时候，停止分向小时进位。校时时钟源可以手动输入或借用电路中的时钟。4. 具有正点报时功能，正点前10秒开始，蜂鸣器1秒响1秒停地响5次。-Digital clock circuit diagram
数字钟
- fpga课程中用vhdl语言编写的数字钟 输出到板子上是，就是一个数字时钟
digital_clock
- vivado 学习资料 数字时钟设计 新建工程后导入相关文件（source）(digital clock Vivado learning materials Digital clock design, new construction, import related documents (source))
disp
- 可以计时，显示时间。这个程序使用10MHz的时钟信号转为1Hz和500Hz的信号作为输入，来驱动显示数码管时间的。(You can clock and display time.)
kcsj
- 利用Verilog层次化设计的多功能数字时钟，可以调时，设置闹钟，仿广播台整点报时(The use of Verilog hierarchical design of multi-functional digital clock, you can set the alarm clock, similar to the broadcast station, the whole point of time)
Digital_Clock
- 用verilog写的数字时钟代码，亲测可用，可自行编写test bench进行仿真(Written in Verilog digital clock code, pro test available, you can write your own test bench for simulation)
clock_shiyan
- 数电课程设计，数字时钟，基于Quartus II设计(Digital electric course design, digital clock)
clock
- 数字时钟，用VHDL语言设计，能调时间，整点响铃(Digital clock, designed in VHDL language, can adjust the time, the whole bell ring)