搜索资源列表
calc
- 用FPGA设计的简易计算器,包括按键模块,数码管模块-Use the FPGA design simple calculator, including key module, digital tube module
VHDL语言写的简易计算器
- 用VHDL写的简易计算器，包括加减乘除，除法器用加法器和乘法器组成-Write simple calculator with VHDL, division, including add, subtract, multiply and divide adder on time-multiplier and used
key_led
- 简易计算器的键盘和LED显示，很简单，但也可以说很复杂-Simple calculator keyboard and LED display, very simple, but can also be said very complicated
verilog_calculator
- 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.
verilog_calculator
- 一个Verilog写的简易计算器。能进行二进制加减乘除运算，操作数通过按键输入并用数码管显示。当按下运算符号键后，计算器进行两个数的运算，数码管将结果显示出来。-A simple calculator written in Verilog. Binary addition and subtraction to multiplication and division, operating a few keystrokes and use digital display. When the pres
calculator--EDA
- EDA可编程逻辑设计 设计一个简易十进制以内的计算器 可以利用按键和数码管作为计算器的输入和输出，能完成十以内的整数的加、减、乘、除（商和余数）运算，预算结果可以是正/负数，结果的绝对值可以超过十，且能够正确显示。-EDA design of programmable logic to design a simple decimal calculator can be used within the tube as the calculator keys and digital inputs a
dog12.31.13.2
- FPGA作品 简易计算器 可以实现加减乘除以及后退等功能-Fpga work can achieve a calculator to add, subtract, multiply and back, except for functions
verilogcalculator
- 简易的计算器，可实现加减乘除运算，采用verilog编写-Simple calculator, addition, subtraction operation can be realized using verilog prepared
calculator
- 简易的计算器，可实现加减乘除运算，采用verilog编写-Simple calculator realized by verilog,which could operate addition and subtraction process
CIII_EP3C40F780C8_37_Calculator
- SOPC,CycloneIII系列芯片EP3C40F780C8，NIOS II IDE,简易计算器实验代码-SOPC,CycloneIII，EP3C40F780C8，NIOS II IDE, CALCULATOR code
Calculator.v
- Verilog实现简易计算器，用数码管显示结果-Verilog achieve simple calculator, with digital display results
EDA_2
- 简易计算器，可四位同时显示，加减法有指示-Simple calculator four also showed that addition and subtraction with instructions
jianyijisuanqi
- 用VHDL实现简易计算器，实现加法、减法、乘法、除法的功能。-Use VHDL to realize simple calculator, can realize the function of addition, subtraction, multiplication, and division.
SBcalculator
- fpga简易二进制输入十进制输出计算器，八位拨码开关输入，四位数码管输出。开发板：Spartan 3E XC3S100E CP132 -5-A simple binary-decimal calculator. Spartan 3E XC3S100E CP132 -5
Caculator
- 基于Verilog语言编写的简易计算器，实现了加减法的运算，有模块和约束文件。-Verilog language based on simple calculator, to achieve the operation of addition and subtraction, there are modules and constraint files.
cal
- 针对CPLD实现简易计算器的程序。全部程序都在了。-cpld cal program
entity-fp-is
- 简易计算器4*4矩阵键盘输入,多个数值vhdl代码-Simple calculator 4* 4 matrix keyboard input, multiple values vhdl codes
FPGA-jisuanqi
- 基于Verilog 语言的简易计算器的程序参考-design of jisuanqi