基于VHDL语言的频率计的设计，可以精确的测试出频率的大小-VHDL language based on the frequency meter is designed to accurately test the frequency of the size of the

vhdl verilog code for alu operation pll,biy sliced processor

以DMA传输方式接收外部串口设备发送的数据并保存到SDRAM存储器中，通过使用串口调试工具来查看数据传输是否正确。-DMA transfer to an external serial device to receive data sent and saved to SDRAM memory, by using the serial port debugging tool to view data transmission is correct.