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wishbone_i2c_master
- -- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on simple_i2c -- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman) -- rev. 0.3 may 4th 200
I2C
- I2C总线大全 I2C器件的操作 I2C总线C语言源程序 I~2C总线串行通信技术及其应用 I2C总线时序分析及其模拟 i2c总线协议(中文版)-Daquan I2C-bus I2C bus I2C device operation C language source code I ~ 2C bus serial communication technology and its applications Analysis and Simulation of I2C Bus T
crc7
- 以crc7为例进行UVM的验证 Part 1: 搭建环境。 本文使用的Quartus II 13.1(64 bit),器件库MAX V。写了一个Verilog的简单的crc7。 仿真环境是ModelSim 10.2c。虽说自带UVM库。但是,没找到Modelsim自带的uvm_dpi.dll,于是,还重新编译了一番。 本文在win 10下。下载uvm-1.1d(现在最新版本有1.2d了),放好。(crc7 code by system verilog language)
Modelsim 10.2c
- Crack of Modelsim 10.2c