搜索资源列表
miniMIPS
- 这是一个基于mips-I结构的处理器,32bit,冯诺依曼结构-This is based on a MIPS - I structure of the processor, 32bit, von Neumann structure
Lab20
- the booth algorithm to implement the 32bits multiplication.-the booth algorithm to implement the 32bit 's multiplication.
NIOS_TFT
- 用Quartus II 8.0（32bit），NIOS编译环境下，用TFT做的一个数码相框，附加原理图和veri-log程序代码-Using Quartus II 8.0 (32bit), NIOS compiler environment, TFT do with a digital photo frame, attached schematic and program code veri-log
alu32bit
- verilog hdl alu module it is 32bit alu and 1bit alu
32_16div
- 这是一个简单的除法器（32bit/16bit),采用移位相减法-This is a simple divider (32bit/16bit), using phase shift subtraction
ALU_ise10migration
- It s vhdl source code for 32 bit ALU.
CPU
- 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
CSLA_32
- 32bit carry select adder
150M
- quartus_nios 综合开发平台，可以多中断，重要的是它的cpu可以工作在150M，总线工作在100M×32bit；-quartus_nios comprehensive development platform that can interrupt more important is that it' s cpu can operate at 150M, bus work in 100M × 32bit
singlecycleMIPS-lite
- mips processor——32bit-mips processor- 32bit
uart_receive
- 串口接收数据44个8bit数据，并且将4个8bit数拼接成32bit数，存进ram中， 可以通过 in system memory editro 查看-Serial port receive data 44 8bit data, and will be spliced into four 8bit number of 32bit number, deposit into the ram in, you can see in system memory editro
booth_mult
- VHDL code for Booth multiplier for 32bit input
pci32lite_oc
- PCI 32bit Slave Verilog 代码-PCI 32bit Slave Verilog code
Adder_Kogge_Stone_32bit_With_Test_Bench
- verilog source code and test bench of Adder Kogge Stone 32-Bit
Multiplier
- verilog implementation of the 32bit multiplier
mips789_latest.tar
- mips789..32bit implementation ...found it on the internet..cyclone EPIC target device
32bitcpu
- 用verilog写的32位CPU源码，通过汇编语言可以实现加减乘除左移右移等运算。并且通过Lookahead算法提高了运算效率，大大节省了运算时间。通过ASC流程可以模拟出其内部电路结构。代码，过程文件，readme在文件夹中-Written by 32-bit CPU verilog source code, assembly language can be achieved through the addition, subtraction and other operations righ
lowpower-multiplier
- 32位无符号低功耗的乘法器,经过10000次测试,用smic.13工艺,DC综合后,延时为8ns,功耗仅为635uw.-it is an unsigned 32bit multiplier.100000 benchmarks have been tested and all of them passed. With smic 0.13um process library, after disign complier analysis, the clock period is 8ns,and th
subtract-for-32bit-floating-point
- subtract for 32bit floating point unit
[Source code] 32bit_ALU_code_verilog
- 32bit ALU project source code