CDN加速镜像 | 设为首页 | 加入收藏夹
当前位置: 首页 资源下载 源码下载 嵌入式/单片机编程 VHDL编程 搜索资源 - Approximation

搜索资源列表

  1. hilbert_transformer_latest.tar

    0下载:
  2. The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hil
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-06
    • 文件大小:1.18mb
    • 提供者:Arun
  1. 85

    0下载:
  2. 逐次逼近的VHDL开平方算法,作者:QQ 64134703 ,电子毕业设计,欢迎咨询 -VHDL open square successive approximation algorithm, the authors: QQ 64134703, e-graduate design, please consult
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-05
    • 文件大小:175.63kb
    • 提供者:黄先生
  1. etd-0407109-183702-81-001[1]

    0下载:
  2. 文章介绍了YUV向RGB颜色空间转换的硬件电路实现算法.在高基乘法算法基础上,建立了参数化高基乘法算法模型,并给出了Verilog HDL描述 小数乘法的整数乘法近似和近似误差给予了详细的讨论.采用乘法单元复用的设计结果将在两个时钟周期内完成YUV向RGB的颜色空间转换.-This paper introduces the YUV to RGB color space conversion hardware algorithm. Matrix multiplication algorithm i
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-14
    • 文件大小:3.81mb
    • 提供者:jjj
  1. ads7809

    1下载:
  2. ADS7809是Burr-Brown公司推出的高精度AD采集芯片。它采用5V单电源供电,内含16位 逐次逼近寄存器,采样精度高,功耗小。 用Verilog实现其配置-ADS7809 is a Burr-Brown Introduces High Precision AD capture chip. It uses a single 5V supply, with 16-bit successive approximation register, sampling and high pre
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-10
    • 文件大小:773byte
    • 提供者:dengxiaosong
  1. EDGELAP

    0下载:
  2. Based on this one-dimensional analysis, the theory can be carried over to two-dimensions as long as there is an accurate approximation to calculate the derivative of a two-dimensional image. The Sobel operator performs a 2-D spatial gradient measurem
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:2.02kb
    • 提供者:siva
  1. sobel_verilog

    0下载:
  2. Based on this one-dimensional analysis, the theory can be carried over to two-dimensions as long as there is an accurate approximation to calculate the derivative of a two-dimensional image. The Sobel operator performs a 2-D spatial gradient measurem
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-03
    • 文件大小:580byte
    • 提供者:siva
  1. ln-function

    0下载:
  2. 利用VHDL编写ln(1+x)这样的特殊函数逼近程序,采用Quartus 仿真-Writing the ln (1+x) special function approximation procedures using VHDL simulation with Quartus
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-03
    • 文件大小:4.43kb
    • 提供者:邱陈辉
  1. zcjj

    0下载:
  2. 该算法使用于AD转换,它是运用EDA技术通过对逐次渐进法进行编程实现的,运算快速,正确率高-The algorithm uses the AD converter, it is the use of EDA technology through programming on a successive approximation method, fast computing, the correct rate
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-28
    • 文件大小:225.3kb
    • 提供者:谭林
  1. SAR-ADC

    0下载:
  2. 这是一个用于实现逐次逼近型ADC的控制程序,用状态机实现的,用的VHDL语言。在实际项目中测试过-This is a successive approximation type ADC control program, written using the state machine tested in the actual project
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-08
    • 文件大小:343.5kb
    • 提供者:jbb
  1. SAR-ADC

    1下载:
  2. Complete Successive approximation Analog to digital converter along with the source code
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-12
    • 文件大小:665.15kb
    • 提供者:Ramya
  1. 1-D-DWT_verilog-code

    0下载:
  2. Image compression is one of the prominent topics in image processing that plays a very important role in reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT for image compression. The compu
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-06
    • 文件大小:1.41mb
    • 提供者:jeason
  1. arctan-Function-Approximation

    0下载:
  2. If we implement the arctan(x) using the embedded 9 × 9 bit multipliers we have to take into account that our values are in the range − 1 ≤ x < 1. We therefore use a fractional integer representation in a 1.8 format.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-29
    • 文件大小:312.82kb
    • 提供者:hooman hematkhah
  1. ADC_SA_8bit

    0下载:
  2. the successive approximation part of the circuit. trial_root is loaded with value 8'b1000_0000 on the rising egde that makes count = 3'b000.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-05-03
    • 文件大小:7kb
    • 提供者:liki20
搜珍网 www.dssz.com