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system 完成远程通信的整体任务
- Verilog，QuartusII可正确运行，可下载到FPGA上，完成远程通信的整体任务，PC发数据，键盘输入运算符与运算数计算将结果显示在数码管上并返回给PC机，需异步串口调试软件-Verilog, QuartusII run correctly, can be downloaded to the FPGA, to complete the overall task of remote communication, PC send data, keyboard operators and op
CORDIC_ATAN.rar
- 使用verilog语言完成了基于cordic算法求反正切的计算，精度为8次迭代,Verilog language used to complete based on CORDIC algorithm for arctangent calculation, an accuracy of 8 iterations
vhdl.rar
- 该pdf 详细的介绍了 浮点小数的计算法则，和在vhdl程序中 浮点小数的表示方法，和乘除法的运用 希望对大家有用,The pdf in detail the calculation of the decimal floating-point rules, and procedures in vhdl decimal floating-point method, and the use of multiplication and division for all of us hope tha
HwLog10.rar
- 用verilog写的，基于查表法实现的LOG10运算器，在Altera FPGA中应用。,It is a verilog design of LOG10 calculation unit, which is based on LUT arithmatic. And it is applicated in Altera FPGA.
crc16
- crc16 module for SDIO DAT line calculation
cpu2
- 另一个简单的16位VHDL的CPU程序~~~包含简单的加减乘除移位等操作，适用于课程设计-Another simple VHDL' s CPU 16-bit program ~ ~ ~ contains simple calculation shift and other operations for course design
QPSKvhdl
- QPSK的vhdl调制与解调，内有详细文档介绍-The vhdl QPSK modulation and demodulation, the document describes in detail
cos
- FPGA实现正弦，余弦的计算，verilog语言-FPGA realization of sine, cosine calculation, verilog language
firshuzilvboqi
- :介绍了基于FPGA的FIR数字滤波器的设计与实现,该设计利用Matlab工具箱设计窗函数计算FIR滤波器系数,并通过VHDL层次化设计方法,同时FPGA与单片机有机结合,采用C51及VHDL语言模块化的设计思想及进行优化编程,有效实现了键盘可设置参数及LCD显示。结果表明此实现结构能进一步完善数据的快速处理和有效控制,提高了设计的灵活性、可靠性和功能的可扩展性。 -: This paper presents FPGA-based FIR digital filter design and
altera_Sine_CosineusingtheCORDICalgorithm
- 计算机算术是微处理器运算的数学基础,其中一个非常重要的部分就是超越函数的计算问题。数学函数的VHDL实现-Computer arithmetic is a microprocessor based on mathematical computing, in which a very important part is the calculation of transcendental function. VHDL realization of mathematical functions
GCD
- 最大公约数的计算,各个源描述的编译顺序:gcd.vhd,gcd_stim.vhd-The common denominator of the calculation, the various sources described in the order of the compiler: gcd.vhd, gcd_stim.vhd
TINY3
- verilog 编写的tiny cpu 代码，可实现简单的指令和计算-Verilog prepared tiny cpu code, can be simple instructions and the calculation
atan_lut
- 基于改进的查找表的arctan计算模块，包含完整的VHDL源代码及部分注释．绝对原创！-Arctan calculation module based on improved searching form. The rar package contains complete VHDL source code and some notes. Absolutely original!
statment
- 在VHDL的设计中用for 语句来实现2 个8 位数的相乘计算。-In the VHDL design using for statement to achieve two-digit multiplication calculation 8.
subadd
- 一个四位二进制加/减运算器。 要求：当控制端G＝0时做加运算，G＝1时做减运算。用发光二极管表示运算结果的正、负。用数码管显示运算结果：加运算时，相加之和不超过15，减运算时，结果可正可负，但都用原码表示。-Plus a four binary/by calculator. Requirements: When the control terminal G = 0 when computing increases, G = 1 when computing reduced. Computin
shop
- 自动售货机控制系统，具有对货物信息的存储，进程控制，硬币处理，余额计算和显示等功能。-Vending machine control system, with information on goods store, process control, coin processing, the balance of the calculation and display functions.
phase-locked
- 主要是关于锁相环的环路滤波设计与计算，非常经典的-Mainly on the phase-locked loop filter design and calculation, very classic
EDA
- 设信号ＣＨ表示计算路程脉冲，每０.１公里变化一个周期．出租车三公里内为起步价７.０元，超过三公里，每公里２.４元．设置一个开车键，停止状态按动一次表示开车，开车状态按动一次表示下车．一个暂停键，暂停是停止收费，再次按动继续收费．七段码显示当前价格和路程．且所有七段码为动态显示． 如果有谁会的话，帮帮忙吧，写些主要的程序就行了-Established that the calculation of CH distance signal pulse, 0.1 kilometers of each
sqrt
- This zip file contains the verilog source code for square root calculation and its test bench
verilog-Division-calculation
- verilog Division calculation verilog 除法计算方法-verilog Division calculation