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gongcehngsheji_477-2
- 使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
juanji2
- 用TI DSP汇编指令进行程序设计：“TIC54XDSP汇编程序设计-卷积-compiled using TI DSP Programming instructions : "TIC54XDSP compilation of program design-convolution
baseband_verilog.rar
- verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器,verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum m
juanjiqi
- 这是一个卷积器的设计，源码值得好好地学习-This is a convolution design, source code should be a good learning
conv3
- Program to implement convolution through VHDL-Program to implement convolution through VHDL...
matlab
- 完成十余卷积过程，简单方便，能够这样那样这样，sorry-Convolution process more than a decade to complete, simple and convenient, this can be done this way, sorry
convolution_calculator_4_bits
- convolution is important and is widely used in digital signal processing.For example, in LTI system. Input two sequences of 8-bit 2 s complement signed numbers with length 2~8. the input values range is -128~127.
juanji
- 采用vhdl语言编写的卷积编码（2.1.7），通过调试可直接下载使用-Convolution using vhdl language code (2.1.7) can be directly downloaded through the use of debugging
EDGELAP
- Based on this one-dimensional analysis, the theory can be carried over to two-dimensions as long as there is an accurate approximation to calculate the derivative of a two-dimensional image. The Sobel operator performs a 2-D spatial gradient measurem
sobel_verilog
- Based on this one-dimensional analysis, the theory can be carried over to two-dimensions as long as there is an accurate approximation to calculate the derivative of a two-dimensional image. The Sobel operator performs a 2-D spatial gradient measurem
VD-vhdl-Code
- this codes are for convolution encoder and Viterbi decoder synthesis and implementation.
convolution
- convolution卷积码生成器程序设计及仿真源代码-convolution convolutional code generator source code of program design and simulation
f
- 为了解决传统的维特比译码器结构复杂、译码速度慢、消耗资源大的问题，提出一种新型的适用于FPGA特点，路径存储与译码输出并行工作，同步存储路径矢量和状态矢量的译码器设计方案。该设计方案通过仿真验证，译码结果正确，得到编码前的原始码元，速度显著提高，译码器复杂程度明显降低,性能优良。-The convolution code
convcode
- 基于Modelsim的卷积码(2,1,7)的Verilog实现，采用直接生成-Modelsim-based convolution code (2,1,7) and Verilog implementation of direct generation
DATA_CONV_ENCODE
- OFDM系统中的多码速卷积码的FPGA实现,可以实现1/2,3/4,2/3等码率!-convolution encoder!
Convolution_filter-fpga
- Implementation of a 2D Convolution Filter on FPGA. Performance evaluation between CPU, GBU and FPGA
convolution
- 卷积 严格遵守时序的一维卷积运算，用testbench测试了-convolution write a VHDL file to compute one-dimensional convolution latency 14
convolution
- Source code for convolution of two complex number is written in Verilog language
Convolution
- 卷积程序的Verilog程序，实现卷积功能(Convolution program Verilog program to achieve convolution function)