搜索资源列表
lxh_xulijianceqi
- 这是1个序列检测器,可以重复检测序列,在通信方面用的较多-This is a sequence detector, can detect repeat sequence, in communications with the more
DJDPLJ_T
- 本VHDL源代码由顶层模块、测频模块、驱动模块、计算模块、LCD显示模块、复位模块组成，能精确检测从1--100M频率，误差极小且恒定。-the VHDL source code from the top module, measuring frequency module, driver modules, modules, LCD display module, reduction modules, can be used to accurately detect from 1 -- 100M
987654
- 能够检测各种状态，能很好的实现功能，很有价值！-to detect a variety of conditions, and can achieve good functional and of great value!
detect
- 一个序列检测器的设计。程序不是问题，关键是理解状态机的编程思想。
up_test
- 基于vhdl语言的源代码，用于检测信号的上升沿，多用于同步时钟-Vhdl source code based on the language used to detect the rising edge, used for synchronous clock
10010
- Verilog状态机设计-10010序列检测器-Verilog state machine design-10010 Sequence Detector
sequence_inspector
- 序列检测器可用于检测一组或多组二进制码组成的脉冲序列信号，这在数字通信领域中有广泛的应用。当序列检测器连续收到一组二进制码后，如果这组码与检测器中预先设置的码相同，则输出1，否则输出0。由于这种检测的关键在于正确码的收到必须是连续的，这就要求检测器必须记住前一次的正确码及正确序列，直到连续的检测中收到每一位都与预置数的对应码相同。在检测过程中，任何一位不相等都将回到初始状态重新开始检测。并附有测试程序-Sequence detector can be used to detect one or
JIANCHE
- 本设计是一个序列检测器，能够检测11位长的系列信号，根据需要可适当扩展其序列长度-The design is a sequence detector, can detect a long series of 11 signals, according to the needs may be appropriate to expand its sequence length
seqdet2
- 状态机实现序列检测VerilogHDL及其仿真-State machine implementation sequence VerilogHDL Detect and Simulation
GBJC
- 平坦度检测中的高度检测算法，使用ISE开发环境，语言为VHDL，平台是XC3S4-a vhdl_program used for flat detect
Multi_Debug_Card
- 利用Xilinx XC2C128（Xilinx CPLD）制做的台式电脑的Debug卡及原理图，对于不开机的主板，能侦测出CPU到北桥之间具体那根信号线空焊，用于快速维修不开机之主板。-The use of Xilinx XC2C128 (Xilinx CPLD) desktop computer system to do the Debug Card and schematic diagram for the motherboard does not boot, can detect the
VCollide201
- 模型冲突检测，是VCollide的压缩文件。能够检测虚拟物体是否发生碰撞，并返回信息-Model of conflict detection is VCollide the compressed file. Can detect whether a collision between virtual objects, and return information
sourcefile
- 在Altera公司的Cyclone系列FPGA开发板上试验的按键中断程序，希望对那些学习中断开发的初学者有帮助。 pio_key.v是verilog编写的按键中断程序，对应四个按键，按其中任何一个键都可以发送一个中断； keyint.c是Nios中编写的C程序，用于检测按键的中断，如果检测到中断，会检测是哪个按键按下，从而执行相应的程序！ -In Altera' s Cyclone series FPGA development board interrupt key test
ptos
- 要求：并行输入1 byte，串行输出，无数据时输出高电平，输出格式1100+8bit+奇偶校验+0011（停止位）串行输入，并行输出，检测是否奇偶校验错误，是否有帧传输错误传输每bit数据占16个clock周期 -Requirements: parallel importation of 1 byte, serial output, no data output high, output format 1100+8 bit+ parity+0011 (stop bit) serial inp
key
- Verilog HDL编写的键盘扫描程序，考虑了判断按键弹起的问题。程序按一定的频率用低电平循环扫描行线，同时检测列线的状态，一旦判断有一列为低则表示有键被按下，停止扫描并保持当前行线的状态，再读取列线的状态从而得到当前按键的键码；等待按键弹起：检测到各列线都变成高点平后，重新开始扫描过程，等待下一次按键。-Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. P
sdmlbeh
- This code implements the behavioral modelling of mealy type sequence detector to detect the sequence 1010. The code is a quartus project file.
sdmlstruct
- This code implements the structural modelling of mealy type sequence detector to detect the sequence 1010. The code is a quartus project file
sdmrbeh
- This code implements the behavioral modelling of a Moore type sequence detector to detect the sequence 1010. The code is a quartus project file
rise-or-fall-detect
- 上升沿、下降沿检测代码,开发语言是verilog HDL，希望对大家有所帮助-rise or fall detect of information and the tool is the software Quartus and the landuage is vrilog HDLthank you for using it hope it will benifit for you
frame detect
- 帧同步搜索电路，检查帧同步所在，VHDL程序-frame detect