搜索资源列表
FPGA_UART
- 用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA
fiber_ctrl
- lattice Diamond平台的千兆以太网光纤接口与GMII接口的转换-lattice Diamond Platform of Gigabit Ethernet optical fiber interface and GMII interface conversion
state_led_one
- 基于verilog HDL的状态机8位流水灯（一个按键控制左转和右转），开发环境Diamond 3.7(64-bit)；FPGA采用LCMXO2-1200HC-4MG132C；时钟25M；开发板：与非网小脚丫-Based verilog HDL state machine eight light water (a key control buttons turn left and turn right), the development environment Diamond 3.7 (64-b
LED_shining
- 实现LED灯交替闪烁，已通过Diamond环境仿真与FPGA硬件测试-LED lights flash alternately implemented, Diamond has passed the test environment simulation and FPGA Hardware
flashled
- 实现LED流水灯，1S1闪，有reset功能，已完成Diamond仿真与FPGA硬件测试-Achieve LED light water, 1S1 flash, reset function has been completed Diamond FPGA hardware simulation and test
Electric_clock
- Verilog数字时钟，已实现Diamond环境仿真与FPGA硬件测试-Verilog digital clock, has achieved Diamond FPGA hardware simulation and test environment