搜索资源列表
vga_hex_disp.rar
- 该项目可在VGA显示器上显示ＲＡＭ或ＲＯＭ中的十六进制数据，使用ＶｅｒｉｌｏｇＨＤＬ语言编写，在ＱｕａｒｔｕｓＩＩ开发环境下验证。,The Project displays the content of memory cells in the form of hexadecimal numbers. It uses RAM and ROM memory modules available through special functions. This is why before compilin
P2S_TOP
- This file contains the Parallel to Serial conversion. This is the top module where we can change the code. The other part of this file is Parallel to Serial controller i,e P2S_SM
SPItoI2S
- 该文件是I2S 转 SPI的Verilog的源代码，可以在此基础上修改成自己的应用代码-The file is transferred SPI, I2S Verilog source code, you can change the basis of their application code into
GAL16V8(fangzhen74LS138)
- GAL16V8(仿真74LS138),试验通过。包括able及jed文件。对pcb印板设计时，对简化走线特别有用。简单的修改GAL16V8程序，可灵活地进行地址译码修改。-GAL16V8 (simulation 74LS138), test passed. Including the able and jed file. Printed on the pcb board design, especially useful to simplify alignment. Simple modific
UART_Receiver
- 将串行数据转换为16为并行数据。可以更改文件中的参数，适应其他位宽和数据长度的接收。-16 the serial data into parallel data. You can change the file parameters and data to adapt the length of the other bits wide receiver.
video_add_program
- 改文件为OPENHW嵌入式大赛的获奖项目，主要做的视频叠加，很有参考价值-Change the file for OPENHW embedded contest winning projects, mainly to do video overlay, great reference value
Example-b8-5
- 学习VCD文件的基本使用方法,四态的VCD文件，参数在0/1/X/Z之间变化，没有信号的强度信息-Learn the basics of using VCD files,Four state VCD file, change the parameters between 0/1/X/Z no signal strength information
decrypt_8
- This file is top level entity of decrypt_8 project. This project is 8_bit decryption for TEA algorithm. You can change number of bits (at least 32 bit for TEA). This project is only for one round. You should use input as encryption output so that you
statled_latest.tar
- a simple module to get the most of your on board heartbeat LED change or add more sequences easily in parameters file
IP_COE_Abs2Rel
- 编程辅助软件，将Xilinx ISE 14.x IP核含有的COE文件从绝对路径改成相对路径-Progrmming assisting software, Xilinx ISE 14.x IP core have COE file absolute path change into relative path
Lvds_lattice
- 这是基于lattice fpga 芯片的 ttl 24bits（rgb888）模块。简单易懂，修改输出分辨率只需要修改几行宏定义。整个工程文件在diamond2.0版本上编译运行。-This is based on ttl 24bits lattice fpga chip (rgb888) module. Easy to understand and modify the output resolution is only need to change a few lines of macro
tinycpufiles
- TinyCPU源码,使用Verilog编写的资源占用极少的CPU。Quartus工程，可跑在Altera MAXII CPLD上,也很方便移植到其他FPGA上。CPU使用200个逻辑单元，外设(SPI,LCD等)使用180个逻辑单元。 内含汇编编译器源码(VC2008)，可编译CPU对应的汇编文件。-The sourcecode of TinyCPU, which only consumed very few logical cells, written by Verilog. It is