搜索资源列表
exp13_7
- 竞赛抢答器:控制8255,C口作为输入,从A口输出与之对应的LED段码-race Responder : Control 8255, C mouth as input, output from the A-corresponding to the code of LED
exp28_20
- C++程序控制8255(C口输入, A口输出)的直流电机-8255 C program control (C mouth input, output A. I) Motor
数据结构c描述习题集答案
- 减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制位数）。 二、设计原理 输入/输出说明： d：异步置数数据输入； q：当前计数器数据输出； clock：时钟脉冲； count_en：计数器计数使能控制（1：计数/0：停止计数）； updown：计数器进行自加/自减运算控制（1：自加/0：自减）； load_d-a counter a reduction, design requirem
multiplier-accumulator(vhdl)
- 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用) -With the VHDL language to describe the design and realization of multiplier-accumulator, four of
miller
- 整个系统分为两个模块：检测模块和解码模块。检测模块主要完成从输入串行序列判断出A，B或C信号，并分别输出脉冲标志脉冲串Signal_A，Signal_B和Signal_C；同时，当检测到任一信号时，BIT_EN_temp输出一个高脉冲。解码模块根据检测模块输出的三个标志脉冲进行0/1解码，输出最终的密勒解码数据DOUT；同时，输出DATA_EN和BIT_EN两个标志信号。-The whole system is divided into two modules: detection module
ca_gen
- 此Verilog程序产生用于GPS卫星导航信号的C/A码，输入信号有时钟、时钟使能、复位、给定的卫星编号，输出产生的C/A码。此程序在代码上进行优化，占用了更少的资源。-This procedure generated Verilog for the GPS satellite navigation signals C/A code, the input signal with the clock, clock enable, reset, given the satellite number,
calc_v2_s3eboard
- Simple calculator EDK design implemented on Digilent S3EBOARD using Microblaze soft-core CPU. Input: PS/2 keyboard, output: VGA monitor.
Priority_Encoder
- Unlike a multiplexer that selects one individual data input line and then sends that data to a single output line or switch, an Encoder takes all the data inputs one at a time and converts them to a single encoded output. Then, it is a multi-input da
Encoder_Using_Assign_Statement
- Encoder Using Assign Statements: Unlike a multiplexer that selects one individual data input line and then sends that data to a single output line or switch, an Encoder takes all the data inputs one at a time and converts them to a single encoded o
Solutions
- `timescale 1ns / 1ps module AND_OR(INP, OUT1) input [3:0] INP output OUT1 wire SIG1, SIG2 MY_AND2 U0 (.A(INP[0]), .B(INP[1]), .C(SIG1)) MY_AND2 U1 (.A(INP[2]), .B(INP[3]), .C(SIG2)) MY_OR2 U2 (.A(SIG1), .B(SIG2), .
circuit_simulate
- c语言写的一个分析电路级别 模拟电路输入输出的小程序 原数字电路用Verilog语言描述-c language to write an analysis of circuit-level analog input and output of small programs of the original Verilog language to describe digital circuits
or1200_wb_ram_gpio_pll
- Quartus ii项目，硬件平台为SOPC2000，能实现LED的各种显示控制及按键输入。包括硬件实现的Verilog及软件实现的C实现。SOPC系统的设计在Windows的quaruts ii 8.0上实现，软件部分在Ubuntu上实现。-Quartus ii project, the hardware platform for SOPC2000, to achieve a variety of LED display control and key input. Including Ver
3-input_majority_detector
- 这是一个3输入多数探测器.它有3个输入（A，乙，丙）和1个输出（Y）-This is a 3 input majority detector.It have 3 input(a,b,c) and 1 output(y)
verilog_testbench_genetator
- 这是一个perl程序 只需要在cmd中运行，参数为你的Verilog名字 功能是:半自动生成Verilog的testbench，提高编码效率-#-----READ ME of verilog_tb_generate.pl----------------------| # | #-----copyright(C) Xzmeng 2010---------------
FPGA-Kai-Fa-Ban.REV2.0
- 本产品教程与注亍NIOS Ⅱ嵌入式开収,主要由C诧言开収,因此,打好C诧言的基础很重要,在此推荐一本《C程序设计诧言》(第2版),英文名为《The C Programming Language》(Second Edition),该书是由C诧言的设计者Brian W.Kernighan和Dennis M.Ritchie编写的一部介绍标准C诧言及其程序设计方法的权威性经典著作。全面、系统地讱述了C诧言的各个特性及程序设计的基本方法，包括基本概念，类型和表达式、控制流、函数不程序结构、指针不数组、结构
jianpan
- 51单片机（C语言） PS2键盘输入1602液晶显示-51 MCU (C language) PS2 keyboard input 1602 LCD
switch_2
- c program for display the output with respect to input taken from keyboard
rotW
- Rotating Wheel is a simple digital circuit which makes use of a Seven Segment Display (SSD). It causes a continuous clockwise/anticlockwise movement of the SSD segments. Also, the circulatory movements are made more realistic by providing momentary o
alu-10-10
- 16位运算器，包含+、-、与或非、移位等功能，内部指定a、b、cin，输入clk与rst，输出16位y与c\z标志位-16-bit arithmetic unit, including+,-, and or, shift and other functions, within the specified a, b, cin, input clk and rst, 16-bit output y and c \ z flag
berlekamp_parallel
- The Berlekamp multiplier [3] uses two basis representations, the polynomial basis for the multiplier and the dual basis for the multiplicand and the product. Because it is normal practice to input all data in the same basis, this means some basis