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add_full_n
- 该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。-the program is to achieve the n-bit full adder, first using the door with non-realization of a family - and finally realize the full n-bit adder.
sub_full_n
- 该程序实现的N位全减器，首先实现一位的减法器，之后实现N位全减器。-Program of the N-bit-wide reduction, the first realization of a subtraction for, after all N-reduction devices.
adderN
- N位加法器源代码，通用的，通过xilinx验证，希望对大家有用。-N-bit adder source code, a common, through Xilinx certification, useful for all.
assignmentP2
- 1. Access the relevant reference books or technical data books and give accurate definitions for the following timing parameters: (1) propagation time tPD, (2) transition time tTD, (3) setup time tSU, (4) hold time tHD, and (5) clock-to
cnt
- 俩个比较好的计数器的vhdl代码：一个是n位通用计数器，一个是的用到的语法比较全面。是比较好的学习资料-Both a relatively good counter VHDL code: one is the generic n-bit counter, one is the syntax used in the more comprehensive. Is a better learning materials
divide
- It is n-bit sequential divider in verilog language
Desktop
- VHDL code for 16 byte ROM & n bit comparator & a full adder
BCD_adder
- VHDL code for a one bit comparator and an n bit register and a BCD adder
tristate
- VHDL code for a full adder and n bit full adder a tri state buffer and a flip flop
jishu10
- FPGA——1位10进制计数程序，可用原理图输入法拓展n位，下载后可直接使用，Q2中综合已通过，基于cyclone-FPGA- 1 station 10 hexadecimal counting procedures, schematics can be used to expand n-bit input, can be used directly after downloading, Q2 has passed comprehensive, based on the cyclone
ALU
- 这个是我的数字电路设计报告，利用了vhdl语言制作了一个n位的可配置alu器件，实现了一些基本的功能，附有完整的报告及代码，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-This is my digital circuit design report, using the vhdl language produced an n-bit alu device can be configured to achieve some basic functions, with
division
- Verilog n-bit Division using datapath and controller for COMPUTER ARCHITECT LAB-Verilog n-bit Division using datapath and controller for COMPUTER ARCHITECT LAB
Priority_Encoder
- Unlike a multiplexer that selects one individual data input line and then sends that data to a single output line or switch, an Encoder takes all the data inputs one at a time and converts them to a single encoded output. Then, it is a multi-input da
m-operand-n-bit-adder
- n bit m operand adder
n-bit
- n bit parity generator is a versatile program that adds parity bits for any length of data the user enters . It accurately adds parity bits on the MSB and solves the problem during any kind of digital communication protocol
N-DtoA-VHDL-AMS
- 下面是一个混合信号的例子,是一个N位D/A转换器的VHDL-AMS描述-The following is an example of a mixed signal that is a N bit D/A converter described in VHDL-AMS
8-bit-Restoring-Divider
- Division is performed in four stages. After reset, the 8-bit numerator is “loaded” in the remainder register, the 6-bit denominator is loaded and aligned (by 2N− 1 for a N bit numerator), and the quotient register is set to zero. In the second a
N-BitComparator
- N-Bit Comparator Between X and Y
N-BitParallelLoadShifRegister
- N Bit ParallelLoadShiftRegister
n-bit adder
- n-bit optimized adder using VHDL