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verilog SDRAM core
- 我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application
(fpga)sdram.rar
- verilog 代码,读写SDRAM 不带仿真,需要自己编写测试文件,Verilog code, read and write SDRAM simulation without the need to prepare their own test documentation
sdram_ctrl1.rar
- FPGA读写SDRAM的VHDL程序,已经测试过,FPGA to read and write the VHDL procedures SDRAM have been tested
sdram-control-verilog
- SDRAM控制器源码,内含完整的控制器verilog源代码和测试代码,超值哈。-This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.
sdram_test
- FPGA测试程序,使用XC3S250E对SDRAM进行读写的测试程序,SDRAM使用的是HY57V281620, 大小为128M。-FPGA test procedure, the use of XC3S250E SDRAM read and write on the test procedure, SDRAM using HY57V281620, size of 128M.
ddrsdram_verilog
- 内附doc是DDR SDRAM 参考设计文档;model包含SDRAM Verilog的模型;simulation包含verilog测试平台、modelsim工程文、设计库函数;source包含verilog源文件;synthesis包含工程的综合文件 。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Verilog model simulation with veri
SDRAM_simulation_model
- sdram的测试程序 和读写程序 vhdl语言编写的-SDRAM testing procedures and to read and write procedures VHDL language
DDRSDRAMControllerverilogcode
- 这个设计是使用Virtex-4实现DDR的控制器的,设计分为三个主要模块:Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Fron
SDRAMcontrollor
- SDRAM控制器,以下是我用VHDL编写SDRAM Controller的全部资料。文档提供的SDRAM控制器能工作在125MHz,我在实际工程中用到了120MHz,但没有再往上做测试了-SDRAM controller, the following is my SDRAM Controller using VHDL to prepare all the information. Documentation provided by SDRAM controller can work in the
sdram
- 程序说明: 本次实验控制开发板上面的SDRAM完成读写功能。 先向SDRAM里面写数据,然后再将数据读出来做比较,如果不匹配就通过LED变亮显示出来,如果一致,LED就不亮。 part1是使用Modelsim仿真的工程 part2是在开发斑上面验证的工程 目录说明: part1: part1_32是4m32SDRAM的仿真工程 part1_16是4m16SDRAM的仿真工程 \model文件夹里面是仿真模型 \rtl文件夹里面是源文件 \sim文
sdramtEST
- sdram动态存储器测试的源文件工程,Quartus II 9.0 (32-Bit)版本。-sdram TEST
SDRAMtest
- 使用quartus软件打开 内含sdram测试文件代码语言为verilog 备注清晰,适合初学者-Quartus software using open source test file containing sdram verilog Remarks clear language, suitable for beginners
DE0_SDRAM
- DE0开发板SDRAM测试程序,10为拨码开关作为数据写入SDRAM中存储,在读出用7段数码管显示-ALTERA DE0 SDRAM
fpgaexperiment_sourcecode
- FPGA实现七个实验的源程序。SDRAM测试,按键及PIO口中断实验,定时器实验,seg7实验,sopc_led实验,flash烧写,fpga_led,锁相环。-FPGA realization of the seven experiments of the source. SDRAM test, test buttons and PIO port interrupt, timer experiment, seg7 experiment, sopc_led test, flash program
SDRAM
- FPGA SDRAM控制器Verilog源码,通过测试-FPGA SDRAM VERILOG
modelsim-sdram-sim
- 包括sdram 测试平台,sdram控制器,sdram行为模型。-Includes sdram testbench, sdram controller, sdram behavior model.
SDRAM
- 用Verilog写的SDRAM测试程序。先向SDRAM里面写数据,然后再将数据读出来做比较。-Written using Verilog SDRAM test program. Xianxiang SDRAM write data inside, and then read out the data for comparison.
SDRAM
- 使用VHDL语言编写的对SDRAM进行读写操作控制器及其简单的测试层序。(VHDL language used to read and write operations controller SDRAM and its simple test sequence.)
SDRAM缓冲测试程序
- 对FPGA的SDRAM进行测试,主要是实现FIFO-SDRAM-FIFO的数据传输(Test the SDRAM of the FPGA)
FPGA读写SDRAM的实例
- FPGA对SDRAM进行读写测试程序,亲测有效无误。(FPGA reads and writes test programs for SDRAM.)