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immediate_divide_module
- 用组合逻辑实现循环除法器。稳定、安全、可靠。-Combinational logic loop divider. Stable, secure, and reliable.
HASH-code-implementation-using-VHDL
- implementation for Secure Hash Algorithm 1 SHA-1 in vhdl language contain no test file.
FPGA-Design-Security-Solution
- This document provides a solution to prevent the FPGA designs from being copied. It allows the FPGA design to remain secure even if the configuration bitstream is captured
A3P40_ProASIC3
- ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3 devices the advantage of being a secure, low-power, sing
A_PUF_Design
- 基于fpga的物理不可克隆函数（PUF）模块的实现-A PUF Design for Secure FPGA-Based Embedded Systems