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BER_examination
- 基于FPGA的伪随机序列误码率检测，包括随机序列的发生，随机序列的接收统计。-FPGA-based pseudo-random sequence of bit error rate testing, including the occurrence of random sequence, random sequence to receive statistics.
PN4
- 语言：VHDL 功能：该PN4序列的特点为将一个4位序列的前两位取异或，再让序列左移一位，用异或的结果作为序列的最后一位。序列周期是15，即15位伪随机序列。其中包括序列的产生模块和检测模块。对于误码检测，首先捕获相位。然后，规定测试的码的总个数，统计这些码中有多少个不能满足PN序列特点的，用计数器统计个数。如果发现误码过多，可能是相位失调，重新捕获相位，再进行误码检测。 仿真工具：modelsim 综合工具：quartus -Language: VHDL function:
keilc-shiyan3
- 单处机实验程序，实现数据统计及排序实验 熟悉单片机的指令系统，了解程序设计基本方法1、 排序用冒泡排序算法-One experimental program at the machine, data statistics and sort familiar to microcontroller instruction experiment to understand the basic method of 1 programming, sorting using bubble sort al
Taximeter-VHDL
- 使用硬件描述语言编写的一段出租车计价程序，对里程、计价、等待计价做出统计和显示-Written using a hardware descr iption language Taximeter procedures, mileage, pricing, waiting to make pricing and display statistics
testspeed
- 红绿灯实时变换程序，在接到信号时对该路车流量进行统计，一个高电平代表一辆车。并能对两条路的流量进行比较计算，根据比较百分比输出相应数值电平。-Transformation process in real time the traffic lights, after receiving the signal for the road traffic statistics, a high level representative of a car. And is able to compare th
main
- 统计文档中出现某个人名的频率 适合于词频统-Statistics document the frequency of a person s name for the word frequency statistics
VHDL_Ethernet
- VHDL实现的以太网测试仪器，可以根据配置生成各种模式的以太网数据报文，并对接收到的以太网数据进行统计。-VHDL realization of Ethernet test instrument can generate a variety of modes depending on the configuration of Ethernet data packets, and receives Ethernet data statistics.
r
- 统计8位矢量中‘1’的个数（分别用变量和信号两种方法实现）-Statistics of 8 bits of the number of 1 in the vector
Calender
- 万年历，可以准确统计并显示当前的年月日等日期时间-Calendar, you can have accurate statistics and displays the current date and time date etc.
EDA
- 我的EDA课程设计 Verilog HDL 自动售票机的实现 ·设计目标： 本设计完成基于Verilog HDL的自动售票系统，综合软件用Quartus II8.1。 本自动售票系统可以完成1元、2元、3元、4元四种票的自动售出，货币种类可以是1元、5元、10元、50元、100元，能自动找零和显示 ·总体设计： 共有四个主要模块和一个顶层模块：四个模块分别是主控模块、统计模块、出票模块和找零模块；顶层模块负责各模块间的连接，组成一个可用的自动售票系统。-My EDA
i2s_latest
- Details Name: i2s Created: Mar 22, 2004 Updated: Jan 10, 2014 SVN Updated: Mar 10, 2009 SVN: Browse Latest version: download Statistics: View Other project properties Category: Communication controller Language: VHDL De
verilog_cordic_core
- A highly configurable 1st quadrant CORDIC core in verilog-Details Name: verilog_cordic_core Created: Sep 14, 2008 Updated: Aug 12, 2011 SVN Updated: Mar 10, 2009 SVN: Browse Latest version: download Statistics: View Other projec
counter
- 实现技术功能，由待测信号触发使能，在时钟clk的控制下统计计数。-Technological functions, is triggered by the measured signal is enabled, under the control of the clock clk statistics count.
FPGA
- 韩福柱老师FPGA实验源码，用vhdl语言在xilinx FPGA上实现，包括ad采集，温度传感器读取，秒表，跑马灯和按键次数统计4个实验-Han Fu teacher FPGA column experiment source code, vhdl languages on xilinx FPGA implementations, including ad acquisition, temperature sensor readings, stopwatch, marquees and key
uikuh
- Mainly for data analysis and statistics, Prediction Error Method for Parameter Identification - the idea of relaxation, Classic GLCM texture calculation method.
mpjcy
- Including regression analysis and probability and statistics, Modern signal processing jobs when the graduate, Matlab for beginner students will help.
4486
- Includes the modulation, demodulation, signal to noise ratio calculation, Including regression analysis and probability and statistics, Suppressed carrier type differential phase modulation.
nf045
- Rotating machinery 2-d holographic spectrum calculation, Including regression analysis and probability and statistics, Minimum mean square error MSE calculation algorithm.
lan_v75
- Various resource allocation algorithm, Example tracking mean cheap, Mainly for data analysis and statistics.