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expi
- Vhdl实现计算exp功能 在apex20k上经过验证-Vhdl achieve in terms exp function on proven apex20k
altpll0
- 锁相环的使用 可以倍频或者分频 可以最多四个输出-Your use of Altera Corporation s design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programmin
vhdl-Jijin
- 关于VHDL语言的设计例子集锦，对于初学者来讲非常合适，可以对比自己的程序来找出更好的设计思路-On the VHDL design language allehanda example, in terms of very suitable for beginners, you can contrast their own process to identify a better design ideas
vhdl_manygoodmodel
- VHDL例程集锦，有很多例子，从简单的逻辑例程到复杂的微操作系统和相关存储器。-This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examples range from simple combinationa
verilog_HDL_examples
- 本书介绍了大量verilog HDL程序设计的实例，对于verilog语言学习者和从事相关工作的工程师来说，都有一定的学习和参考价值。-The book introduced the verilog HDL programming a large number of examples, the verilog language learners and engineers engaged in related work both in terms of learning and a certai
compact_config
- Altera provides a number of reference designs that show efficient solutions for common design problems. Altera® reference designs can be used to develop new solutions and innovative products, improve your understanding of Altera product capabilit
book
- Verilog HDL与VHDL都是数字系统设计的硬件描述语言，VerilogHDL适合算法级，rtl，逻辑级，门级，而VHDL适合特大型的系统级设计。针对这些特点这两本书深入浅出的介绍了这两种语言。-Verilog HDL and VHDL design of digital systems is the hardware descr iption language, VerilogHDL suitable algorithm level, rtl, logic level, gate-lev
NIosII
- NIosII软处理器快速入门,内容挺详细的，至少对我这种初学者而言-Quick Start NIosII soft processor, the contents of very detailed, at least for beginners in terms of my
jop
- ALL VHDL FPGA -- THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF -- MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
spiflashcontroller
- -- This program is free software you can redistribute it and/or -- modify it under the terms of the GNU General Public License -- as published by the Free Software Foundation either version 2 -- of the License, or (at your option) any later ver
61EDA_D825
- 该设计针对SMB总线进行的控制操作，包括控制，接口及仿真文件-THIS DESIGN IS PROVIDED TO YOU “AS IS”. XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, N
EDAtechnologies
- 此为本人学习VHDL语言时的笔记，内容非常详细，对于初学EDA技术的人来讲是很好参考知识。其中包括简单的编程和较复杂的编程，很有用的东西。-This is my notes when learning VHDL language, the content is very detailed and EDA technologies for the beginner who is a good reference in terms of knowledge. These include simple
VHDLsample
- 英国诺森比亚大学的vhdl语言例程集锦，英文原版。 包含很多优秀的VHDL语言范例，可供学习。所有程序均可在符合IEEE标准的模拟器上模拟。-This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The exampl
sdram_yadmc.tar
- /* * Yet Another Dynamic Memory Controller * Copyright (C) 2008 Sebastien Bourdeauducq - http://lekernel.net * This file is part of Milkymist. * * Milkymist is free software you can redistribute it and/or modify it * under the terms
lab3
- VHDL Lab 3 – Arithmetic & State Machines In this lab we will look at arithmetic circuits that add, subtract, and multiply numbers. Each type of circuit will be implemented in two ways: first by writing VHDL code that describes the require
verilogsram
- 深入浅出玩转FPGA一书中实验中的SDRAM读写实验-Fun FPGA simple terms, a book to read and write experimental test of the SDRAM
verilogiic1121
- 深入浅出玩转FPGA一书中实验中的II2C读写实验-Fun FPGA simple terms, a book to read and write experimental test of the II2C
MULTIPLE_CORE
- 硬件乘法器，其基础就是加法器结构，它已经是现代计算机中必不可少的一部分。[1]乘法器的模型就是基于“移位和相加”的算法。在该算法中，乘法器中每一个比特位都会产生一个局部乘积。第一个局部乘积由乘法器的LSB产生，第二个乘积由乘法器的第二位产生，以此类推。如果相应的乘数比特位是1，那么局部乘积就是被乘数的值，如果相应的乘数比特位是0，那么局部乘积全为0。每次局部乘积都向左移动一位。 -64-bit multiplier design experiment is the first in the HK
Ms32pci
- PCI-ip硬件描述语言-开源的，可以做参考设计，如果需要的话，-This models are written in VHDL! Author is Ovidiu Lupas! MASTER model generates PCI compliant signals checks Target signal compliance with PCI checks data received from Target for correctness generates
AssignmentP6
- 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA. (1) Synthesize and verify (simulate) the VHDL design of the FIFOs (2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells)