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Convolutional encoding and Viterbi decoding with k
- 卷积码编码和维特比解码 当K为7 时 供大家参考Convolutional encoding and Viterbi decoding with k 7 rate 1 2 -convolutional coding and Viterbi decoding when K 7:00 for reference convolutional encoding and Viterbi decoding with k 1 2 7 rate
viterbi
- 介绍了viterbi译码器的编解码器的设计，包括decoder.v,encoder.v.control.v,ram.v等，压缩 包里面有pdf说明
viterbi
- 卷积码编码及其Viterbi译码的实现
viterbi
- 一个完整的viterbi编码程序，使用vhdl语言编写，还有测试程序
(2,1,3)卷积码编解码
- (2,1,3)卷积码编解码，viterbi译码
Viterbi_IP.rar
- viterbi译码器的IP核，可以直接编译使用,viterbi decoder IP core, the compiler can directly use
viterbi.rar
- 这是一个用VERILOG HDL语言编写的viterbi译码程序,This is a language VERILOG HDL by the viterbi decoding process
viterbi
- verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
Viterbi
- 实现VHDL的维特比译码 -VHDL Viterbi decoding to achieveVHDL Viterbi decoding to achieve
ViterbiDecodeK9R12HardDecision
- viterbi 硬判决译码，基本实现了（2，1，9）卷积码的硬判决译码，用modelsim RTL仿真通过-hard-decision viterbi decoding, the basic realization of the (2,1,9) convolutional codes hard decision decoding, using modelsim RTL simulation through
husw
- 用VHDL语言设计维特比 解码器 是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
Viterbi
- Viterbi译码器的FPGA实现代码,来在国外大学论坛.-Viterbi decoder implementation of the FPGA code to the Forum at foreign universities.
viterbi
- Viterbi verilog generator
viterbi
- viterbi decoder with convolutional encoder
viterbi
- verilog code for viterbi encoder and decoder
viterbi
- 对于语音信号的Viterbi算法的简单仿真实现 在QuartusII下-Viterbi algorithm for speech signals simple simulation to achieve in the next QuartusII
viterbi
- This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is w
viterbi
- 硬判决viterbi译码的硬件实现，通过verilog语言。采用回溯的方法。回溯深度为16.-Hard decision viterbi decoding in hardware, through the verilog language. A retrospective approach. Back depth is 16.
viterbi
- 高效率的viterbi译码，对通信中的卷积码进行译码-Efficient viterbi decoding of communications for decoding convolutional codes
（2,1,3）卷积编码和viterbi译码
- 自己写的（2,1,3）卷积编码器和viterbi译码，测试已通过