搜索资源列表
RISC8.ZIP
- 简单的一个8位RISC，Verilog HDL代码,类型为pic16c57-a simple eight RISC, Verilog HDL code, the type of pic16c57
SS7160.ZIP
- 该代码为配合7号信令模块MK50H27的cpld(xilinx 95144)的逻辑代码,其中包括了VHDL及原理图.-the code to meet on the 7th of signaling modules MK50H27 cpld (Xilinx 95144 ) logic code, which included a schematic and VHDL.
CALCULAT.ZIP
- verilog源码，可实现两位的加法器，在xillinx foundation 3.1下验证通过-verilog source, the two can achieve Adder, In xillinx foundation 3.1 certification through
SPI_Core.ZIP
- SPI协议的VHDL/Verilog语言实现。-SPI agreement VHDL / Verilog language.
Sobel--Image_Filter_An_Image_filtering_VHDL
- Sobel--Image Filter (I). An Image filtering is made over data loaded into the on board RAM and presented on a VGA monitor.zip-Sobel -- Image Filter (I). An Image filteri Vi is made over the data loaded into RAM on board a nd presented on a VGA monito
MMM_SRC.ZIP
- DOS下开发网络程序的SOCK库,有示例程序,包括FTP，ＨＴＴＰ，ＳＭＴＰ服务程序的源代码
an-103005-vgagen
- an-103005-vgagen.zip是一个VGA显示控制器，是verilog HDL 编制的
xst3_video
- xst3_video.ZIP是基于XILINX的XST3开发板的视频采集源码，里面有SDRAM control
wsmcu51btl_exe
- VHDLram控制器vhdl程序lib_06.zip
LCD_HD44780.ZIP
- xilinx 器件vhdl原程序，LCD控制
70V631_VHDL_Model.zip
- 针对IDT公司71v631的fpga设计，VHDL语言模型。
MICO8_DEMO_03_18_08.ZIP
- Lattice 超精简8位软核CPU--Mico8，开放所有源代码，包括VHDL，编译器，支持GCC编译器。可在Lattice所有FPGA和MachXO 器件上使用。本例包含示例和说明文档。对使用Lattice器件的用户或者学习CPU设计的人员有较高参考价值。,Lattice super-streamlined eight soft-core CPU- Mico8, open up all the source code, including VHDL, the compiler to supp
ethernet.zip
- 以太网控制器VHDL实现以及相关参考文档，超有使用价值，请仔细阅览,ethernet MAC controller VHDL realize
web_cpu88.zip
- Intel微处理器8088的VHDL实现，可以用ModelSim进行仿真测试。,Realization of intel microprocessor 8088 in VHDL language, and can be tested and simulated with ModelSim.
VHDL语言实现的arm内核
- 5个ram核，arm6_verilog,arm7_verilog_1,arm7_VHDL,Core_arm_VHDL,nnARM01_11_1_3 arm6_verilog.rar 一个最简单的arm内核，verilog写的，有点乱 arm7_verilog_1.rar J. Shin用verilog写的arm7核心，结构良好，简明易懂 nnARM01_11_1_3.zip.zip nnARM开源项目，国防科技大学牛人ShengYu Shen写的，原来放在opencores上，
RISC8.ZIP
- verilog RISC8 cpu CORE 8位RISC CPU 内核源码（VERILOG 版）-verilogRISC8 cpu CORE8-bit RISC CPU core source (VERILOG version)
xapp851
- The xapp851.zip archive includes the following subdirectories. The specific contents of each subdirectory below: \rtl - HDL design files \sim - simulation files \synth - Synthesis related files \par - Place/Route related files-The xapp
CVI.ZIP
- Program for neon controller, for creating and downloading to a I2C flash-Program for neon controller, for creating and downloading to a I2C flash
FTChipID_LV7.zip
- FTChipID_LV7.zip
基准电路ISCAS`89.zip
- 基准电路ISCAS`89.zip包含了 基本所有的S电路 和C电路，已经在做项目的使用了，没有任何的错误，欢迎大家下载，学习和相互交流。