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fifo
- 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
ADPCMverilog
- ADPCM编码的Verilog编码实现，代码有详细的注释，编译通过-ADPCM coding Verilog code, the code has detailed notes, compiled by
ima_adpcm_encoder_latest.tar
- This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by defau
ADPCM
- APPCM算法和AD/DA芯片驱动在CPLD中的实现，已在实际硬件中测试OK，quartus2环境-APPCM algorithm and AD/DA chip in the drive to achieve in the CPLD has been tested in actual hardware OK, quartus2 environment
fifo
- 同步FIFO 创建一个256x8大小的同步FIFO，并通过串口发送数据初始化FIFO，FPGA内部读取FIFO的数据通过窗口发送到PC-FIFO
ADPCM
- ADPCM ENCODER and DECODER
ADPCMCodec
- The DVI Adaptive Differential Pulse Code Modulation (ADPCM) algorithm was first described in an IMA recommendation on audio formats and conversion practices [1]. ADPCM is a transformation that encodes 16-bit audio as 4 bits (a 4:1 compression ratio).
ADPCMEncoder
- ADPCM encoder with ICON, VIO, ILA, working on Xilinx ISE and chipscope.
ADPCMDecoder
- ADPCM decoder working on Xilinx ISE 12.2 code includes core ICON ILA VIO test on chipscope
adpcm
- 用verilog实现adpcm语音编解码其功能，有测试程序，通过了仿真。-adpcm made by verilog. have been tested.
conv_12_adpcm
- adpcm编码verilog程序,包含pcm转换模块、adpcm编码输出模块-ADPCM coding verilog procedures, including PCM conversion module, ADPCM encoding output module
code
- ADPCM解码器,4位adpcm音频数据解压缩成16位的pcm数据，采样频率为20KHz.-ADPCM decoder