搜索资源列表
mcpu_1.06b
- MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD - one of the smallest available programmable logic devices. While this CPU is not powerful enough for real world applications it has proven itself as a valuable educational tool. The source
asfpga_v1.00e.tar
- asfpga is an assembler written for use in FPGA design. It can be easily modified for your instruction set. The ultimate goal of this software is to allow a FPGA designer to easily write assembly code for a custom instruction set.
c16_latest.tar
- c16 ucore. this a 16 VHDL cpu core. complete with Assembler and C compiler. All src code included.-c16 ucore. this a 16 VHDL cpu core. complete with Assembler and C compiler. All src code included.
servomat
- antidad_a EQU s0 talto EQU s1 Rename register sX with <name> tbajo EQU s2 indicador EQU s3 cantidad_b EQU S4 Define constant <name>, assign value name ROM output file generated by pBlazIDE assembler VHDL "ROM_form.vhd", "ser
pipelined_computer
- 基于de2-board的汇编以及verilog的五段流水线CPU代码，适合新手学习-Based on the de2-board assembler, and the five-stage pipelined CPU verilog code, suitable for novice learning
cpu
- 8位实验CPU设计利用设计好的指令系统，编写汇编代码，以便测试所有设计的指令及指令涉及的相关功能。设计好测试用的汇编代码后，然后利用Quartus II软件附带的DebugController,编写汇编编译规则。接着，利用DebugController软件把汇编编译之后的二进制代码置入到所采用的存储器中，并对设计好的8位CPU进行测试。-Eight experiments designed CPU design using the instruction set, write assembly
tinycpufiles
- TinyCPU源码,使用Verilog编写的资源占用极少的CPU。Quartus工程，可跑在Altera MAXII CPLD上,也很方便移植到其他FPGA上。CPU使用200个逻辑单元，外设(SPI,LCD等)使用180个逻辑单元。 内含汇编编译器源码(VC2008)，可编译CPU对应的汇编文件。-The sourcecode of TinyCPU, which only consumed very few logical cells, written by Verilog. It is
hamming
- verilog语言实现一个CPU，汇编程序实现汉明编码功能，输入11位代码，输出15位编码结果。(Verilog language to achieve a CPU, assembler to achieve Hamming coding function, enter 11 bit code, output 15 bit encoding results.)