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经典设计VHDL源代码
- 非常好的VHDL小程序。内容齐全。基本的功能都有。-very good VHDL small programs. Content complete. The basic functions have.
430VS串口
- 给予MSP430F147的串口通讯程序,能帮助你了解MSP430系列单片机和串口通讯的基本方法-give MSP430F147 Serial communication process can help you understand the MSP430 MCU serial communications and the basic methods
Verilog DHL数字钟
- 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock
100vhdl例子
- 100vhdl例子 应用于各基础电路或高级电路的基础部分-100vhdl example of the basic circuit used senior circuit or part of the foundation
cpu
- 用VHDL语言设计简单的CPU，重点设计微操作代码，然后设计CPU各组成模块，最后根据设计的微操作设计微指令，验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the f
fft3
- 是用verilog写的FFt源码，通过编译基本是正确，希望对大家有所帮助-Is written FFt verilog source code, compile basic right, we want to help
verilog_codes_for_UG
- Verilog Basic Codes for Beginners -Verilog Basic Codes for Beginners .....
basic-language-elements
- basic VHDL language elements
vhdl-basic-design-flowchar
- vhdl 基礎設計流程 包括一些基本描述語言架構-vhdl basic design flowchar Including some of the basic architecture descr iption language
Char5-basic-arithmetic-logic-models
- 夏宇闻著作：从算法设计到硬线逻辑的实现,CHAR5：基本运算逻辑和它们的Verilog_HDL模型-XIA Wen works: from algorithm design to hard wire logic implementation, CHAR5: basic arithmetic logic models and their Verilog_HDL
Basic-Knowledge-of-Verilog-HDL
- 该讲稿从两个方面介绍了verilog HDL的基本知识： 1.verilog HDL的基础语言知识, 2.verilog-XL仿真 -Basic Knowledge of Verilog HDL
basic.program.vhdl
- example for basic program in vhdl
Basic-Programing-in-CPP
- Examples of basic programing in C-Examples of basic programing in C++
Basic-system-of-nexys3
- the basic system of nexys3(soft core)
The-VHDL-various-basic-code
- VHDL的各种基本代码 包括4选1,8选1多路选择器，8位全加器，加1减1计数器，序列检测器，异步清零16位加减可控计数器，数码管扫描程序，双2选1，状态机等基本程序！-VHDL basic code including 4 election 1,8 to 1 multiplexer selector, 8-bit full adder, plus 1 minus 1 counter sequence detector, asynchronous clear 16 plus or minus
verilog_HDL-basic-course
- verilog的精简教程，很容易看懂，包括了verilog的基本语法和一些基础例子-streamlining verilog tutorial, very easy to understand, including the basic verilog syntax and some basic examples
basic-vanding-code
- basic vandig code vhdl
the-basic-presentation-of-VerilogHDL
- VerilogHDL扫盲文介绍Verilog的基础知识-the basic presentation of VerilogHDL
The-basic-design-of-the-flip-flop
- 1、了解基本触发器的工作原理。 2、进一步熟悉在Quartus II中基于原理图设计的流程。 - The basic design of the flip-flop
design guideline for verilog basic circuit
- basic circuit design based on verilog