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jtag.tar
- jtag的verilog 代码 包含boundary ce
helloworld-ce
- Tensilica开发平台实例，此工程项目文件可用Xtensa软件打开。
shift_register
- -- DEscr iptION : Shift register -- Type : univ -- Width : 4 -- Shift direction: right/left (right active high) -- -- CLK active : high -- CLR active : high -- CLR type : synchronous -- SET active : high -- SET type : synchronous
tdoa123
- Position location services will not only provide new customer options and products for wireless carriers, but will also provide features that could di erentiate services in di erent markets (i.e., di erentiation between PCS, cellular, and special
FPGAandDSP_Builder.pdf
- 某重点大学内部培训verilog和hdl的手册(用于电子竞赛),非常详细具体,对于初学者来说有非常大的帮助-House training a key university and hdl verilog manual (for electronic contest), very detailed and specific, for the beginners have a very big help
ce
- 51单片机程序代码可以共享，需要的继续练习-51 microcontroller code can be shared
ce
- 测试用的程序，初学verilog语言，接触FPGA。希望有能人联系我，谢谢哦。-Test procedures, beginners verilog language, contact FPGA
XU-LIE-JIAN-CE-QI
- 用状态机实现序列检测器的源代码，用maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-State of mind achieved with a sequence detector source code, run the software with maxplus Pin has been configured, the chip is EP1K30TC144-3
新建文件夹
- verilog语言编写的硬件定时器，测试功能可用(Verilog yu yan bian xie de ying jian ding shi qi, qin ce gong neng ke yong)
运动目标检测
- 通过fpga开发板控制ov7670摄像头检测目标 实现运动检测(shi xian yun dong jian ce .)