搜索资源列表
verilogHDL.rar
- 采用有限状态机（要求“三段式”）的方法设计一个带异步清零端的同步可逆模6计数器。同时提供单数码管数字显示和3LED状态显示两种显示方式。,Finite state machine (request, quot Threequot) approach to design a client with Asynchronous Clear reversible synchronous counter module 6. At the same time providing a single digit
TX
- 1路视频光端机的发射端，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES-The launch of a video PDH client, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
counter10
- 带LDN的的同步的预置数端子，并且带CLR的异步清零端-LDN synchronization with the preset number of terminals, and cleared with CLR Asynchronous client
FPGAPROGRAMCHAPTER6
- FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节，然后把它接收回来。 -FPGA development board to write the Verilog code: function is from the client computer sends a byte, and then receive it back.
pcm
- 在光纤通信系统中，光纤中传输的是二进制光脉冲"0"码和"1"码，它由二进制数字信号对光源进行通断调制而产生。而数字信号是对连续变化的模拟信号进行抽样、量化和编码产生的，称为PCM（pulse code modulation），即脉冲编码调制。这种电的数字信号称为数字基带信号，由PCM电端机产生。-In optical fiber communication systems, fiber-optic transmission of light pulses is a binary "
Arbiter
- Arbiter unit includes client and server units. Used for Arbitation of multipliers in Altera FPGA based project. The code supports several multipliers and several clients with different priorities.-Arbiter unit includes client and server units.
T13_USB
- 本示例为基于FPGA红色飓风一代IDS-EP1C6/12开发板的USB传输，实现了pc端接收来自FPGA开发板的数据，并显示条纹，具体使用说明见解压后的说明文档。-This example is based on red hurricane generation FPGA development board' s USB transfer IDS-EP1C6/12 realized pc client receives the data from the FPGA development
pli_socket_example_pc
- vpi/pli socket example code-co-verification using TCP/IP socket (hardware model : verilog+ vpi as server) (software as a client)
infrared-transfer-of-VHDL
- 使用硬件描述语言 VHDL 编程： 红外线传输系统包括发送方和接收两端，都可以单独进行初始化清零处理。在可以设置准备发送的 8bits 8bits8bits 的数据信息，连同一个偶校验位起发送。接受端收到 的数据信息，连同一个偶校验位起发送。接受端收到 8bits的数据信息和一位偶校验后，显示接 收到并根判定的数据信息和一位偶校验后，显示接 收到并根判定的数据信息和一位偶校验后，判定收到的信息是否出错。-Infrared transmission system including the s
serial-pc-verilog
- 串口 和 pc 端通信的verilog程序 ！适合初学者 ！ 代码简单 ，结构清晰！-Serial and pc client communication verilog program! Suitable for beginners! The code is simple, clear structure!
ml605_pcie_x4_gen2
- 使用与xilinx的ml605套件的pcie核程序，芯片 型号是v6系列的4通道的pcie设计。内部包括pcie ip核和用户端程序。已亲测。-Xilinx ml605 using the kit pcie nuclear program, chip model is v6 series of 4-channel pcie design. Internal including pcie ip core and client programs. It has been pro-test.
seg70
- 适合fpga，verilog初学者。按一定的频率轮流向各个数码管的COM端送出低电平，同时送出对应的数据给各段。以动态扫描方式在8位数码管“同时”显示0 7-According to certain frequency in turn to various digital tube COM client sends out the low level, at the same time to send out the corresponding data to the paragraphs.In
qv036
- Complete class-based image processing, contains all of the source code, auto image, There is a well attenuation curve as input to calculate its seismic waves, Transceiver contains two client programs.
Altera+OpenCL
- Altera的OpenCL主要面向信号处理类应用的客户，是用C语言开发FPGA的利器，开放计算语言(OpenCL)联盟著名的公司有FPGA巨头Altera、两大显卡GPU巨头AMD、英伟达、CPU巨头Intel、软件和服务器巨头IBM以及全世界最大的公司Apple（苹果）等等。不过AMD和英伟达是用GPU实现的OpenCL并行运算，Altera是用FPGA实现并行运算。(Altera's OpenCL is mainly a client for signal processing applic