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pn127
- 这是个128位的串行伪随机码发生器，还可以进一步扩充-128 This is a serial pseudo-random code generator, can be further expanded
RAM
- 用VHDL编写一个字长16位，容量128B的RAM控制实现程序，并进行设计综合和功能模拟 。含源程序，及实验要求。适合初学者学习使用。-VHDL prepared with a 16-bit word length, 128B of the RAM capacity to achieve process control and design of analog integrated and functional. Containing source code, and experimental
12864
- 基于VHDL语言，控制液晶12864显示的源程序，非常好用。-Based on the VHDL language, control of liquid crystal display source code 12864, very easy to use.
LcdDisp
- 128*64点阵LCD的Verilog代码，LCD为左右半屏各64*64个点，LCDdatasheet可参考ZY12864D.pdf-128* 64 dot matrix LCD, Verilog code, LCD screen is about half of the 64* 64 points, LCDdatasheet refer ZY12864D.pdf
pcm
- 码率为1000kb/s，字长为8 位、帧长为128 个字、帧同步码为 EB90EB90H 的PCM 采编器-Rate is 1000kb/s, 8-bit word length, frame length is 128 words, frame synchronization of PCM code EB90H editorial control
PLD091205
- DSP2407与128*64LCD显示器接口译码PLD代码-DSP2407 and 128* 64LCD display interface code decoding PLD
PCM
- 本例设计一个码率为500kb/s，字长为8 位、帧长为128 个字、帧同步码为EB90H 的PCM 采编器。用VHDL语言实现的。-This designs a code to lead for the 500 kbs|s, the word is long for 8, the growing is synchronous code of for 128 words and for the EB90 H of PCM adopt to weave a machine.Use what VHDL
fft128
- This 128 point fft code in verilog-This is 128 point fft code in verilog
ram128
- This 128 point code written in verilog-This is 128 point code written in verilog
uploaded-code
- 1.密码生成器，将128个比特的源码编为密码输出并可以实现循环操作。 2.ARM测试从机，是ARM9的一个测试从机，端口配置正确，并已用于实际工作中。-A password generator, 128 bits of source code compiled for the password output and cycle operation can be achieved. 2.A testbench for ARM.It is a testbench of the ARM9,the
CoreFIR_RTL-3.0
- actelIP核 的fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algori
AES_verilog
- 对AES算法加密解密的Verilog源代码，可以实现其128位和256位明文密文之间的转换。-AES algorithm for encryption and decryption of Verilog source code, can achieve the conversion of its 128 and 256 between the plaintext ciphertext.
Coding Files
- We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of United States has been widely
aes128-hdl-master
- Verilog AES hdl key 128 bit code and decode
aes_128pprm3
- 基于PPRM3S盒的128位AES密码算法Verilog代码(Verilog code for 128 bit AES cipher based on PPRM3S box)