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This VHDL code pertains to the DCO model
- code.doc C.1 DCO LEVEL 2 This VHDL code pertains to the DCO model descr iption in Section 6.5.5. The entity declaration of the level 2 DCO is between lines 18 and 39. The VHDL generics or elaboration-phase parameter constants are declared between
5B6B
- FPGA的5B6B编译码器的设计代码可以编译而且有波形图 -5B6B code is used in fiber optic digital communication systems a more extensive line pattern! Data are 5B6B encoding and conversion, and string after the fiber transmission, serial code sequences in continuous bit 0 or b
delay_line
- 延迟线模块的verilog代码，延迟线模块是数字电路设计常用的模块-Delay-line module Verilog code, delay-line module is commonly used in digital circuit design module
interweave_1
- 用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入，按列读出的方法实现。主要包括：信源信号产生（20位的m序列），交织器，解交织器。为实现流水线的操作，采用了两个交织器和两个解交织器，当一个写入数据的时候，另一个读出数据。-Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by colu
VHDL
- 一个实现整数分频的VHDL代码，只要把n设置成你所需要的分频的数值就行-A realization of an integer divider of the VHDL code, as long as the n set you need the sub-frequency values on the line
PLL
- PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上； 顶层文件是PLL.GDF-Digital phase-locked loop PLL is the design source code, which, Fi is the input frequency (receive data), Fo (Q5) is
lift.vhd
- 用VHDL实现了电梯的模拟程序，实现了自动判断楼层，然后根据客户需求和楼层最近原则，实现自动判断上下行，还有报警，强制开门等功能-Achieved using VHDL elevator simulation program, to determine the realization of an automatic floor, and then based on the principle of demand and the floor recently, automatically dete
FIR_Direkt_BAB_P
- VHDL编写的代码。采用流水线方法实现的FIR滤波器。22阶。Fa=48kHz, Fc=10KHz。可用ModeSim仿真并FPGA实现-Code written in VHDL. Line method using the FIR filter. 22 bands. Fa = 48kHz, Fc = 10KHz. Can be used to achieve ModeSim simulation and FPGA
code
- 代码文件夹： ARVI_FSM.v为顶层文件，用于模拟时用。 dataHex.dat 为模拟输入文件（只有10行，象征的意思。实际我们模拟时，dataHex.dat文件足有1个多GB） dataFormat.dat为输入文件对应的带格式的文件 使用modelsim模拟时，将dataHex.dat名字改为CPUContext.txt 结果: result.txt -Code folder: ARVI_FSM.v for top-level documen
lcd12864_1
- lcd12864的显示汉字程序源代码，共四行，每行8个汉字。-Chinese lcd12864 display source code, a total of four lines, eight characters per line.
ami_encoder
- This a vhdl code for Alternate Mark inversion line coding, it is used for baseband transmission.-This is a vhdl code for Alternate Mark inversion line coding, it is used for baseband transmission.
Priority_Encoder
- Unlike a multiplexer that selects one individual data input line and then sends that data to a single output line or switch, an Encoder takes all the data inputs one at a time and converts them to a single encoded output. Then, it is a multi-input da
Encoder_Using_Assign_Statement
- Encoder Using Assign Statements: Unlike a multiplexer that selects one individual data input line and then sends that data to a single output line or switch, an Encoder takes all the data inputs one at a time and converts them to a single encoded o
hdbn
- vhdl语言实现hdb3编码，也可就行hdb2编码，综合后实现hdb3编码的硬件实现-vhdl language hdb3 coding, also may line hdb2 code, after the realization of integrated hardware encoding hdb3
5b6b
- 5B6B码是光纤数字通信系统中使用比较广泛的一种线路码型! 数据经过5B6B编码和并串转换后在光纤上传输，串行码序列中连续的比特0或比特1的长度不超过5，数据在0和1之间变换的密度很高,并具有直流平衡的特性，有利于接收电路和时钟恢复电路的设计。-5B6B code is used in fiber optic digital communication systems a more extensive line pattern! Data are 5B6B encoding and conver
iso9141_xapp365_Automatic_Scanner_Tool
- ISO9141 Automatic Scanner Tools VHDL code
lock-and-lcd
- 基于博创实验箱UP-CUP-FPGA2C35-Ⅱ和Verilog HDL硬件描述语言，分为按键输入模块、LED指示灯模块及LCD显示模块，采用按键BTN1、BTN2作为输入端输入四位密码与事先设定的密码进行匹配，由D1、D2、D3、D4四盏LED灯来指示输入密码的位数。开机时，LCD显示“HELLO! WELCOME!Enter the code:当”，密码输入正确时，LED灯D7亮，同时在实验箱LCD显示屏上显示字符串“Good! Well done!you are right!!!”，当密码
Source-Code-PR5
- simple program for the line follower with using PIC 16f690
code
- 某数据传输系统，试图利用300-3400Hz的话音通 道进行载波传输，波形信道为加性高斯白噪声信道。 –采用线性传输，收发两端拟采用滚降系数0.5的根 号升余弦滤波，以解决采样点失真问题。 –以下仿真采用无记忆采样信道模型，其中受器件限 制，复基带采样点平均功率受限为1，复基带采样 点噪声功率为可调参量-A data transmission system, trying to use 300-3400Hz voice channel for carrier transmission, wave
FPGA-VGA-interface-code
- 针对显示器VGA接口通信FPGA的Verilog源代码，主要包括VGA行扫描和帧扫描模块-Verilog source code for communication VGA interface communication, including VGA line scan and frame scan module