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e7v4
- 数字钟：显示，设置时间，设置闹铃（报时），秒表。 平台：quartusII 5.1。 说明：此版本中已将系统时钟调快，自己稍微改动一下即可，小小的考验，做出来会更有成就感！-digital clock：display time, set time, set alarm(use speaker to alarm), stopwatch. platform: quartusII 5.1 comment: there s a place to change if you want th
tutorial
- 计数器 平台：Xilinx ise 10.1 说明：和ise10.1快速帮助手册配套的源码，适用于初学者。-counter platform: Xilinx ise 10.1 comment: supplement to ise quick start tutorial 10.1, suitable for freshman to fpga and ise software.
s3esk_startup
- 利用kcpsm3控制lcd显示 平台：ise 10.1， picoblaze， Spartan3e 开发板 说明：综合按键和lcd、led的功能，思想简单，需要新技术，适合想在fpga方面深造的人。-using kcpsm3 for lcd display platform: ise 10.1， picoblaze， Spartan-3E FPGA Starter Kit Board comment: involve lcd/led/switch, simple mind bu
fifo-VerilogHDL
- 利用VerilogHDL语言编写的同步FIFO，异步FIFO的编写及其注释-VerilogHDL language using synchronous FIFO, asynchronous FIFO, write and comment
LCD1602
- LCD1602控制器，液晶显示控制模块。VHDL代码。comment是自己加的-LCD1602 controller
LCD-with-comment
- Simple code to display using 8051 interfacing with LCD 2x16
EMP1270
- vhdl spi通讯十分好用，可以对AD7634进行spi通讯！-vhdl spi comment
pinlvji
- 用汇编语言设计的频率计，注释较详细，适于初学者学习使用-Assembly language design frequency meter, the comment in more detail, suitable for beginners to learn to use
USART
- RS232串口通信的VERILOG代码，包含了测试文件，及参数文件，用户只需要修改参数文件里的参数即可满足不同的应用需求；由于串口逻辑比较简单，程序中没有注释；-RS232 serial communication VERILOG code contains the test files and parameter files, users only need to modify the parameters in the parameter file to meet different app
50M-1
- VHDL语言。。如何实现50MHz分频为1Hz，的用意应该是考核你的4M如何分出来，注意看我的注释-VHDL language. . How to achieve 50MHz sub-band is 1Hz, the intention is assessing your 4M how to sub-out, pay attention to my comment
FIFO
- FIFO在VHDL上的实现。没有注释，较为完善，已通过编译。-FIFO implementations in VHDL. No comment, more perfect, has compiled.
Verilog-code
- 关于一些经典的外国verilog HDL代码的总结。非常经典，可以作为初学者学习之用。-Summarize about some classic foreign verilog HDL code. Contains the comment section.
revisions-sur-la-conception-VHDL
- cours VHDL comment on va apprendre la programmation vhdl
Serial_port_modul
- 串口通讯的Verilog程序，用于FPGA控制串口进行数据发送，接收，包含一个串口模块和一个进行调试的主控模块，主控模块可以随意自我设置，串口模块是固定的，全部程序都经过调试，都带有注释，很清晰。-Verilog serial communication program for FPGA control serial data to send, receive, including a serial debugging module and a control module, control m
fulladder.v
- 自己写的full adder的verilog代码，请大家下载。如果有问题请评论给我-Write your own full adder verilog code, please download. If you have questions, please give me a comment
spi_4_2ch
- FPGA spi接口源码，可实现两个从机，扩展后可快速实现多从机，设置灵活，简单方便，有注释-FPGA spi interface source code, can achieve the two slaves, after expansion can quickly achieve multiple slaves, set flexible, easy to use, there is a comment
Altera_exercise
- this vhdl code for altera using quartus II v14 developed for beginners of altera fpga. if any comment or difficulty feel free to ask friends -this is vhdl code for altera using quartus II v14 developed for beginners of altera fpga. if any comment or
qiufouying
- Various resource allocation algorithm, Code, there are very complete notes and explanations The Chinese have a comment, understand it.
wf663
- Welcome to download the study, Including quaternion various calculations, The Chinese have a comment, understand it.