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sdram
- sdram控制器 这里考虑将SDRAM控制器结合目前项目开展来做相应的模块，而不做SDRAM通用控制器，这样也是考虑了FPGA的器件资源而采取的措施。同时编写的逻辑简单，没有多余的逻辑资源有利于提高控制器的速度，满足最后的设计要求。-SDRAM controller here consider SDRAM controller current projects do the corresponding module, but not so common SDRAM controller, a
占空比1：1的通用分频模块
- 用vhdl实现占空比1：1的通用分频模块，非常实用，欢迎大家下载-use VHDL to achieve the common 1:1-frequency module, a very practical and you are welcome to download
EPP
- 并口的EPP协议，与外部的FIFO的empty,full信号共同控制数据传输-of EPP parallel port agreement with the external FIFO empty, full common control signal data transmission
arith_lib-1.0
- 包括所有常用算法：加权计算，进制转换，常用数据编码等，大约共有源代码80个。-include all commonly used algorithms : weighted basis, the base for the conversion, common data coding, source code, a total of about 80.
program_all
- 此文件里为我多年收集的子程序模块源代码，对于初学者很适用。用多种语句描叙，有常用的基本电路模块描叙。-this document for many years I collected subroutine module source code, the application for beginners. Using a variety of statements depicts a common basic circuit module depicts.
FPGAprogram1
- 常用键盘消抖模块——VHDL源程序！！！对vhdl编程的人具有很大的帮助，不可不看 -common keyboard Consumers shaking module -- VHDL source! ! ! Right VHDL programming of great help, I can not s
adderN
- N位加法器源代码，通用的，通过xilinx验证，希望对大家有用。-N-bit adder source code, a common, through Xilinx certification, useful for all.
66vhdl_src
- 66个vhdl的常用源代码，包括有双向口、状态机等，自解压后看vhdl_example.html列表说明.exe-66 vhdl common source code, including the two-mouth state machine, Since unpacked see vhdl_example.html tabulated. exe
wave_genarator_vhdl
- vhdl波形发生程序.实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 各种波形的线形叠加输出。 -vhdl waveform occurred procedures. 4 achieve common sinusoidal waveform, 1.30, sawtooth, square-wave (A, B) the frequency and amplitude control
byvhdstopwatchl
- 1.高精度数字秒表（0.01秒的vhdl语言实现） 2.具有定时，暂停，按键随机存储，翻页回放功能； 3.对30M时钟分频产生显示扫描时钟 4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔，可控性高。 5.模块化设计，其中的许多函数可以成为vhdl语言的通用经典例子（包含分频电路设计，动态扫描时钟设计，译码电路设计，存储器设计，存储回放显示设计）-1. High-precision digital stopwatch (0.01 seconds vhdl la
gcd
- 欧几里得算法求最大公约数电路的Verilog实现，消耗功率较低-Euclid algorithm for the realization of the common denominator Verilog circuit, lower power consumption
FPGA-common-modules-design-
- “CPLDFPGA常用模块与综合系统设计与实例精讲”这本书的工程，均是采用VHDL语言来完成-" CPLDFPGA common modules and integrated system design and examples of Jingjiang," this book works are done using VHDL language
FPGA-common-warning
- FPGA常见警告，适合参考解决编译问题，十分实用-FPGA common warning, compiled for reference to solve the problem, very useful
Analysis-Of-The-Dvb-Common-Scrambling-Algorithm.r
- Analysis of the DVB Common Scrambling Algorithm (DVB-CSA) on FPGA implementation. Performance and Security.
sevenmux(Common-Anode)
- seven segment common anode program in 8051
VHDL-common-errors
- 本文给出了vhdl仿真的常见错误及其有交效的改正措施-VHDL common errors
common-mul
- 常用乘法器设计,有详细的步骤-Common multiplier design；
Verilog-codes-for-common-use
- 包含了几乎所有常用的Verilog的代码，方便所有初学者学习-It includes most codes of Verilog for common use and it is convenient for green hands
Common-adder-design-fpga
- 常用加法器设计,用FPGA实现，任何版本都能实现-Common adder design
Common-multiplier-design
- 常用乘法器设计，用FPGA能实现，值得下载。-Common multiplier design, FPGA can achieve, it is worth downloading.