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LatticeMico8_v3_0_Verilog
- The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose r
VHDL
- 分频跑马灯数码管示范代码能实现分频跑马灯数码管示范-Crossover Marquee digital control Model Code
EDA2
- 学习数控分频器的设计、分析和测试方法。数控分频器的功能就是当在输入端给定不同输入数据时，将对输入的时钟信号有不同的分频比，数控分频器就是用计数值可并行预置的加法计数器设计完成的，方法是将计数溢出位与预置数加载输入信号相接即可。-NC crossover study design, analysis and testing methods. NC divider function is that when the input given different input data, input th
VHDL_fre_div
- 使用VHDL进行分频器设计 本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设 计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过Synplify Pro或FPGA生产厂商的综合器进行综合，形成可使 用的电路，并在ModelSim上进行验证。-For crossover design using VHDL This paper describes the use of ex
miaobiao
- 用VHDL实现的秒表功能，包括分频器，动态显示模块-VHDL implementation with stopwatch functions, including crossover, dynamic display module
Fenpin
- 基于VHDL语言时钟晶振48Mhz的分频器的制作能够实现1HZ分频的时钟信号。-48Mhz clock oscillator based on VHDL language to achieve the production of crossover frequency of the clock signal 1HZ.
jyfp
- 将输入1kHZ的信号分频为50HZ的分频-1kHZ the input signal frequency is 50HZ crossover device
div
- 这是一个基于CPLD的VHDL语言的分频例程-This is a CPLD-based crossover routine VHDL language
Practica-4
- vhdl code: crossover
clk_div
- 任意整数分频器，通过改变参数，可设置所需要的分频频率和占空比-Arbitrary integer divider, by changing the parameters, you can set the desired crossover frequency and duty cycle
pinlvji
- 六位数字频率计的设计程序，包括管脚的分配，分频设计，显示设计-Six digital frequency meter design process，Pin assignment, crossover design, display design
fpq
- 基于fpga的分频器设计，完整代码及工程-Fpga-based crossover design, the complete code and engineering
ipfp
- 基于fpga的分频器设计，利用ip核做的，完整工程及代码-Fpga-based crossover design, using the ip nuclear, complete engineering and code
Verilog_div_frequency
- 本文使用实例描述了在 FPGA/CPLD 上使用 Verilog进行分频器设计，主要包括50 占空比的奇数分频. -This article uses the example describes the crossover design using Verilog in FPGA/CPLD, including the 50 duty cycle odd divider
011-clk_div_pro
- verilog写的一个分频器，利用控制字累加方式，经测试可用-verilog to write a crossover, the control word can be used incrementally, tested
myproject
- 开发环境ISE，使用VHDL语言实现了任意整数分配的分频器，又有一个信号可以控制左转右转的流水等。-Development environment ISE using VHDL language to achieve arbitrary integer assigned crossover, there is another signal control Zuozhuanyouzhuan running water, etc..
VHDL-divider-design
- VHDL分频器设计，本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。-VHDL divider design, this article describes use cases, including even divide, non-50 duty cycle and 50 duty cycle odd divider, half integer (N+0-cr
The-clock-points-frequency-module
- 对外部晶振50M进行分频，分出1M、1k和1的频率-External crystal oscillator fifty m for crossover, ceding 1 m, 1 k and 1 frequency
div
- 一个简单的分频程序，适合初学者了解这一编程语言的特点-A simple crossover procedures, suitable for beginners to understand the programming language
Crossover-design
- 在Altera DE2-70的开发板上实现分频计设计。-In the Altera DE2-70 development board to achieve crossover meter designs.