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VHDL-ROM4.基于ROM的正弦波发生器的设计
- 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 ,ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), wav
BmpToMif
- 通过vhdl定制rom完成的彩灯点亮 -Custom rom vhdl completed by lantern light
spi_controller
- SPI控制器，基于VERILOG描述，分模块设计，共6个模块，时钟产生模块，移位模块，主模块，从模块，定义模块，顶层模块。-SPI controller, based on the VERILOG descr iption, sub-module design, a total of six modules, clock generation module, shift module, main module, from the modules, custom module, top modul
sin_rom(4wzh)
- 基于Quartus II 的信号发生器，通过定制LPM_ROM元件产生正弦波、方波、锯齿波、三角波，分频模块、频率控制模块、按键控制换波形、按键防抖-Quartus II-based signal generator generated by custom LPM_ROM component sine, square, sawtooth, triangle wave frequency module, frequency control module, button control for wa
saolei
- 基于FPGA的扫雷游戏，9X9扫雷，我们的游戏包含有五个状态，分别欢迎界面，游戏胜利，简单游戏模式，自定义游戏模式，游戏失败模式。-FPGA-based minesweeper game, 9X9 mine, the game includes five of our state, respectively, the welcome screen, the game is victory, a simple game modes, custom game modes, game failure
SOPC_pwm_source
- 在SOPC下制作自定义部件（PWM发生器）的源程序，包括硬件描述HDL文件和驱动程序文件-Produced in the SOPC custom component (PWM generator) of the source, including hardware descr iption HDL files and driver files
asfpga_v1.00e.tar
- asfpga is an assembler written for use in FPGA design. It can be easily modified for your instruction set. The ultimate goal of this software is to allow a FPGA designer to easily write assembly code for a custom instruction set.
electric-8.08
- The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including: * Custom IC layout * Schematic Capture (digital and analog) * Textual Languages such a
pwm_source
- Altera官网上关于SOPC中自定义组件（PWM）的实例，官网上现在没了。。可很多书上都在用-Altera in the official line on the SOPC custom component (PWM) of the examples are not the official line. . Can be a lot of books are in use. . .
pwm_hw
- sopc nios ii学习资料介绍niosii 开发自定义外设pwm的verilog源代码-Learning sopc nios ii information on the development of custom peripherals niosii the verilog source code pwm
Hardware_Speedup_DSP_FPGA
- 现场可编程门阵列（FPGA）已经不再单纯应用在芯片与系统之间的直接互联层，在软件无线电（SDR）中，FPGA逐渐用做通用运算架构来实现硬件加速单元，在降低成本和功耗的基础上提升性能表现。SDR调制解调器的典型实现包括通用处理器（GPP）、数字信号处理器（DSP）和FPGA。而且，FPGA架构可以结合专用硬件加速单元，用来卸载GPP或DSP。软核微处理器可以结合定制逻辑，扩展其内核，也可以将分立的硬件加速协处理器添加到系统中。此外，还可将通用布线资源放在FPGA中，这些硬件加速单元可以并行运行，进
cycloneIII3c120dev
- This document describes the hardware features of the Cyclone® III development board, including detailed pin-out information to enable you to create custom FPGA designs that interface with all components of the board.-This document describes the ha
mbtutorial
- This tutorial guides you through the process of using Xilinx Embedded Development Kit (EDK) software tools, in which this tutorial will use the Xilinx Platform Studio (XPS) tool to create a simple processor system and the process of adding a cust
CRC_outputlogic
- custom crc generater(verilog/vhdl)
firfilter
- FIR滤波器：自定滤波器的类型（低通，高通或带通）、设计指标（通带截止频率、通带波纹、阻带截止频率、阻带衰减） 1、根据指标选择合适的窗函数，用窗口设计法设计符合指标的FIR滤波器；并验证其性能是否满足预定指标。 -FIR filters: Custom filter types (low pass, high pass or band-pass), design specifications (passband cutoff frequency, passband ripple, st
spartan_labview_8_driver
- The LabVIEW FPGA for SPARTAN 3E XUP driver was developed to enable educators to use LabVIEW FPGA to teach digital and embedded design concepts. This driver is for educational use and cannot be used on custom FPGA hardware.
spartan_labview_2009_driver
- The LabVIEW FPGA for SPARTAN 3E XUP driver was developed to enable educators to use LabVIEW FPGA to teach digital and embedded design concepts. This driver is for educational use and cannot be used on custom FPGA hardware.
Avt3S400A_Eval_MB_I2C_temp_v10_1_00
- This tutorial shows how to use an IIC controller with MicroBlaze. The IIC controller is connected to a Texas Instruments TMP100 temperature sensor. A custom application with code to communicate with the temperature sensor is used to exercise the
How-to-build-a-custom-FPGA-board
- How to build a custom FPGA board
Custom-IP-to-a-hardware-design
- EXCD-1 可编程片上系统 实验例程 EDK部分 功能：定制一个IP 到硬件设计-EXCD-1 programmable system on chip test routines EDK some of the features: a custom IP to hardware design