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zuosr8
- Picasa 是Google提供的一个 Windows 应用程序;用户可以借助于该程序,在数秒钟内找到自己计算机上的图片,加以编辑并进行欣赏。-Picasa is the Google of a Windows application; Users can aid the process, in just a few seconds to find their own pictures on the computer, edit them and appreciate.
bargraph3layer
- l-edit layout file of a bargraph
abc
- cpld 的频率计的编程,利用程序编辑一个可变频率频率计-cpld programming frequency meter, use the procedure to edit a variable frequency frequency meter
drom
- FPGA rom硬件语言文件 用于输出正弦序列数字信号--- megafunction wizard: ROM: 1-PORT -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: drom.vhd -- Megafunction Na
Support-TP-CCIN-2012-2013
- VHDL编辑PGCD的文件。实际上,这是上课时候老师给的。求通过验证-VHDL edit file of PGCD. In fact, this is the teacher gave during the class. Requirements through validation.
jianyijiafaqi
- 采用MAX+PlusII工具编辑设计的Verilog程序设计的简易加法器。可实现10以内的加法计算-Using MAX+PlusII tools to edit the design of Verilog design of a simple adder. Can be realized within 10 addition calculation
bw_scoresource
- This the bowling score source code. Edit tool is xilinx corp ISE. I used the Modelsim for simulation.-This is the bowling score source code. Edit tool is xilinx corp ISE. I used the Modelsim for simulation.
pci1
- 如果想为了以后的2k平台兼容就最好编wdm,因为windows2k不支持vxd,而且以后的发展wdm肯定要代替vxd了。不过由于我找到的资料基本上都是介绍vxd的,感觉vxd的技术好像更成熟一点,编的人更多一点,所以偷了一下懒(惭愧),就没有去研究wdm,就选择了vxd。-If you want to later edit 2k on the best platform compatible wdm, because windows2k not support vxd, wdm and futu
UpDownCounter
- This is an Up Down Counter coded in Verilog HDL. You can edit the bus width of this.
Norflash
- 用verilog hdl写的Norflash控制器,可实现单字节读写,扇区擦除。-Norflash controller edit by Verilog hdl,it can read or write by Byte,or erase the sector.
sp6ex1
- 时钟二分频实例,详细介绍ISE中如何新建工程、创建并编辑源代码文件、进行语法检查、调用ModelSim进行功能仿真。-Clock two examples, detailed introduction of how to create a new project in ISE, create and edit the source code files, syntax checking, call ModelSim function simulation
pic10
- 本文件夹里面的是实现pic10 CPU的全部verilog代码以及相应的测试脚本代码,当然有一些模块是在quartus中直接编辑波形测试的,所以没有响应的测试脚本文件。 tri_state_port的测试还未完成,test_pic10_status_reg.vt和test_pic10_tri_state_port2.vt都没有完成测试任务 其中有三篇文档: PIC10_RISC_Design.pdf:原文(verilog代码基本都来自原文,对一部分进行了改进),这篇文章写