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b60jian2
- 60进制减法 相比较 代码效率高 可以进行级联-60 compared to 229 subtraction efficient code can be concatenated
LEDDisp
- 8位7段LED显示源码，扫描显示，稳定高效-seven of the eight LED source, scanning, stable and efficient
Evita_Verilog
- 一个高效的FPGA学习入门软件，Evita - 互动VHDL Verilog教学程序.rar-An efficient FPGA software study entry, Evita- Interactive VHDL Verilog teaching procedures. Rar
i2c-verilog
- 可进行i2c读写操作I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable-it can write and read codes in i2c.I2C is a two-wire, bi-directional serial bus that provides a
fuzzyip
- 这是一个我写的关于模糊控制的IP核，简单高效，其中包括寄存器文件等非常全面。-This is a fuzzy control I wrote about the IP core, simple and efficient, including.
verilog_risc
- RISC状态机由三个功能单元构成：处理器、控制器和存储器。 RISC状态机经优化可实现高效的流水线操作。 RISC 中的数据线为16位。 在数据存储器中的0到15的位置放置16个随机数，求16个数的和，放在数据存储器的16、17的位置，高位在前 对这16个数进行排序，从大到小放置在18到33的位置 求出前16个数的平均数，放在34的位置 基本指令有NOP, ADD, SUB, AND, RD, WR, BR,BC。 因为采用16位指令，有扩充的余地。-RISC
38
- 程序提供了一种高效简单的38译码器的算法，非常实用-Procedure provides a simple and efficient algorithm decoder 38, a very practical
chuanrubingchu_jicunqi
- 程序提供了一种简单高效的并入串出寄存器的算法，非常实用-Procedure provides a simple and efficient string into a register algorithm, very useful
trafficlight
- 程序提供了一种简单高效的模拟交通灯控制器的算法，非常实用-Procedure provides a simple and efficient simulation algorithm for the traffic light controller, very useful
Wallace
- 一个关于Wallace树乘法器的论文，当中展示了一种改进后的wallace树乘法器方案，相比原来占用晶体管更少，效率更高-Wallace tree multiplier on the papers, which show an improved wallace tree multiplier after the program, compared to the original transistors occupy less efficient
3970988VHDL
- 关于VHDL中常常会用到的一些小程序，代码效率很高，值得推荐。-About VHDL often used in a number of small procedures, the code efficient, it is recommend.
prbsforip
- 本文设计了一种简捷而又高效的伪随机序列产生方法，最后通过统计对比，说名这种方法产生的随机序列不仅周期长 还具有两好的随机特性-This paper designed a simple and efficient method for the selection of pseudo-random sequence, and finally through statistical comparison, saying that this method of random sequence gen
sin_sample_clock
- EP2C CYCONLY 系列的FPGA时钟测试程序，是由内部时钟分频后，点亮数码显示灯来证明的。绝对好用的程序。编写的执行效率很高-EP2C CYCONLY series FPGA clock test procedure is determined by the internal clock frequency, the lamp lit digital display to prove. Absolute-to-use program. The preparation of the imp
compact_config
- Altera provides a number of reference designs that show efficient solutions for common design problems. Altera® reference designs can be used to develop new solutions and innovative products, improve your understanding of Altera product capabilit
RS204_188
- 可以省去开发者编写译码器的时间，高效的译码器给开发者带来便利-Save developers time to prepare decoder, efficient decoder to facilitate developer
Multiple
- 高效的乘法器设计，既节约面积，又提高性能，同时减少开发周期-Efficient multiplier design, both to save space and improve performance while reducing the development cycle
EfficientSynthesizableFiniteStateMachineDesignusin
- 高效的同步有限状态机的设计，本代码详细的说明了如何设计高效和规范的fsm设计-Efficient Synthesizable Finite State Machine Design using NC-Verilog
fpga
- 为学习FPGA设计人员提供一些经验，提高FPGA使用效率，-For learning FPGA designers to provide some experience and improve the efficient use of FPGA,
Writing-Efficient-Testbenches
- Documents for verilog. (Writing Efficient Testbenches.pdf)
1.Area-Efficient-Carry-Select-Adder
- Area efficient carry save adder