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maxshiyan
- 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital d
time_display&alarm_clock
- 此为在实验板上通过的时钟闹铃程序，源码分别用ASM和VHDL描叙，但两程序功能不同。-this experiment for the board through the alarm clock procedures were used ASM source VHDL and depicts, but the two procedures different functions.
add_sub_lab2
- 实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。-experiment include the operation of a half adder, full adder, plus / subtraction device, and the use of logic diagram VHDl descr iption, including analysis and reporting.
FPGAdigitaltimer
- 本设计要实现一个具有预置数的数字钟的设计,具体要求如下: 1. 正确显示年、月、日 2. 正确显示时、分、秒 3. 具有校时,整点报时和秒表功能 4. 进行系统模拟仿真和下载编程实验,验证系统的正确性 -designed to achieve this with a number of preset clock design, and specific requirements are as follows : 1. Display correctly, , 2. d
mnxhjc
- 本实验用DA转换＋比较器的方法对外界模拟信号进行检测，同时这种联合装置加上CPLD可以代替低频AD转换器的功能。-this experiment + DA conversion method of comparison to the outside world analog signal detection, while such joint CPLD devices can be replaced with low-frequency AD converter functions.
smxsqddl
- 本实验只为了解教学系统中8位八段数码管显示模块的工作原理，设计标准扫描驱动电路模块.-this experiment only to understand the teaching system eight eight LED Display Module principle, design standards scanning drive circuit module.
ps2_and_VGA_and_verilog
- ps/2键盘输入的字符在VGA上进行显示. 本示例是将ps/2键盘输入的字符在VGA上进行显示。在做此实验之前最好先学习PS2键盘接口。-ps / 2 keyboard input of the characters in VGA on the show. This example is to ps / 2 keyboard input characters VGA website on the show. Do this before the experiment started lear
vhdl_traffic
- 模拟交通灯实验 模拟路口的红黄绿交通灯的变化过程，用LED 灯表示交通灯，并在数码管上显示当 前状态剩余时间。-simulation experiment simulated traffic lights junction of red, yellow, and green traffic lights to the process of change, said LED lights for traffic lights, and the digital tube display th
vhdl_dial
- 拨码开关实验 拨码开关8 位0 1 状态在8 位7 段数码管相应位上显示0 或1。-dial-switch dial-switching experiment 8 0 1 state in seven of the eight corresponding digital control-show or a 0.
vhdl_buzzer
- 蜂鸣器实验 向蜂鸣器发送一定频率的方波可以使蜂鸣器发出相应的音调，该实验通过设计一个状 态机和分频器使蜂鸣器发出“多来咪发梭拉西多”的音调。-buzzer to buzzer this experiment certain frequency square wave can buzzer sounded a corresponding pitch. The experiment by designing a state machine and the buzzer sounded a d
FreqCounter
- 一个有效位为4位的十进制的数字频率计,VHDL语言编写，已在硬件实验箱上实验通过。-an effective place to four the number of decimal frequency meter, VHDL language, in the box on the experimental hardware experiment.
TrafficLights_VHDL
- 交通灯信号控制器，VHDL语言编写，已实验通过，具体见RAR注释-traffic signal controller, VHDL language, experiment, see specific RAR Notes
VHDLEXAM
- 我们学校做VHDL实验的源码，在别处是下不到的-our school experiment VHDL source code, elsewhere is less than the
digital_clock
- 用verlog语言编的一个很好的综合实验,特别适合于FPGA/CPLD的初学者-verlog language with a good addendum to the comprehensive experiment, particularly suitable for FPGA / CPLD beginners
Verilog.HDL.Experiment
- Verilog.HDL.Experiment.例程-Verilog.HDL.Experiment. Routine
bch
- Experimental report VHDL VHDL verilog rs flip-flop experiment experimental report VHDL VHDL verilog rs flip-flop experiment
vhdl-experiment-guidance
- 简单易懂的VHDL实验指导,实验环境MAXPLUS Ⅱ-VHDL experiment guidance
multiplier-experiment
- 周立功Fusion StartKit，fpga开发板的实验例程，恒定系数乘法器实验-The ZLG Fusion StartKit, fpga development board test routines, the constant coefficient multiplier experiment
Clock-experiment
- 数字时钟程序，亲自在实验室做过这个实验，实验成功。-Digital clock program, personally done this experiment in the laboratory, the experiment was a success.
Experiment-of-FPGA_DE2
- fpga开发板DE2的实验讲义，讲解的很详细，可作为入门的学习讲义。-Experiment of FPGA_DE2