搜索资源列表
random data gen（vhdl）
- 任意数据发生器的源代码-arbitrary data source code generator
fpgadsp.rar
- system gen & accel dsp 培训资料,system gen & accel dsp
crc-gen
- CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible
ps2lab1
- hex file gen you can get this in any way do it and enjoy it
lock-and-lcd
- 基于博创实验箱UP-CUP-FPGA2C35-Ⅱ和Verilog HDL硬件描述语言，分为按键输入模块、LED指示灯模块及LCD显示模块，采用按键BTN1、BTN2作为输入端输入四位密码与事先设定的密码进行匹配，由D1、D2、D3、D4四盏LED灯来指示输入密码的位数。开机时，LCD显示“HELLO! WELCOME!Enter the code:当”，密码输入正确时，LED灯D7亮，同时在实验箱LCD显示屏上显示字符串“Good! Well done!you are right!!!”，当密码
Sys-gen
- System Generator 多媒体处理算法实现。包含很多实例,是一个提高教程。-System Generator multimedia processing algorithms. Contains many examples, is an enhanced tutorial.
crc-gen[1]
- hamminag code using verilog this code is desinged for detecting
(www.entrance-exam.net)-GEN.-APP
- verilog hdl code for speed control of dc motor
gen_crc
- 任意位宽，任意多项式，并行CRC生成verilog代码脚本-CRC verilog gen scr ipt, for any width of data input
register_test
- This a vhdl code for tseting the colour gen code for fpga-This is a vhdl code for tseting the colour gen code for fpga
register file generation
- the zip file consist of the verilog code which generate the 32 bit reg file so that u can read and write the data into them
3.weigt-pattern-gen
- this IEEE based Vhdl Project accumlator based 3-weight pattern-this is IEEE based Vhdl Project accumlator based 3-weight pattern
gen_div
- 通用偶数分频器，通过输入频率较高的时钟信号，在设置分频参数后，得到较低频率的时钟信号。-gen div
verilog读取bmp图像数据的程序段.txt
- verilog 写的程序段，实现的功能是把bmp图像直接读到数组中。主要是用在仿真过程中，读取图像数据产生video激励用。 代码是个代码片段，只是读取bmp图像部分。 有分的觉得有用的话赏个分，没分的捧个场啦。(read bmp data to array ,used in video stream gen when sim)
pg058-blk-mem-gen
- blockram的手册，适合开发者使用是xilinx的(Blockram manual, suitable for developers to use, is Xilinx)