搜索资源列表
8899
- 最高优先级编码器，是特别好的东西，好不容易才弄到的．-highest priority encoder, is especially good things, the result of the hard-won.
DE2
- 辛辛苦苦的作品应用于DE2 的 开发。。希望对大家有用。-hard work for Dictyophora development. . We hope that the right useful.
ata_6_DMAIPCORE.tar
- 最新的ATA-六总线协议源代码参考，实现DMA,PIO模式，可挂CDROM,IDE硬盘，CF卡．-the latest ATA-6 bus protocol source code reference, achieving DMA, PIO Mode, can be linked to CDROM, IDE hard drive, CF card.
rs_decoder_31_19_6.tar
- Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
mc8051V1.4
- 8051硬核源码（VHDL），具有全部VHDL代码、测试环境以及说明文档、综合脚本等完整的开发、验证环境，源代码通过ASIC投片，并得到不断完善-8,051 hard-core source code (VHDL), with all VHDL code, testing and documentation, environment, Comprehensive integrity of the scr ipt, such as development, certification, the s
ocidec3_IDE_controller
- 硬盘控制器VHDL源代码，实现了PIO和DMA方式，请支持-hard disk controller VHDL source code and realized the PIO and DMA mode, please support
canbus_vhdl
- 使用方法： 1.拷贝到硬盘，用ISE打开工程文件即可。-Use : 1. Copy to the hard drive, use ISE project documents can be opened.
GenCrc1
- 并口硬盘标准PATA6的CRC效验码的vhdl代码-Parallel hard disk standard PATA6 the CRC code well-tested code vhdl
cpuyuanma1.rar
- 说明：cpuyuanma1是硬布线控制器源代码， cpuyuanma2是微程序控制器源代码。,Descr iption: cpuyuanma1 hard wiring the controller source code, cpuyuanma2 micro-program controller source code.
SRAM
- 使用方法： SRAM编程,拷贝到硬盘，用ISE打开工程文件即可-Usage: SRAM programming, copied to the hard drive, open the project file with ISE can
用LV获取机器CPU和硬盘序列号
- 用LV获取机器CPU和硬盘序列号，labview 8.6版本可以使用-Access to the machine with the LV CPU and hard drive serial number, labview 8.6 version can be used
sgpio_target_v0_3
- sgpio target module, flexible hard drive amount.-sgpio target module, flexible hard drive amount.
sata_device_model
- sata_device_model,对做硬盘控制器的朋友有帮助-sata_device_model, to make the hard disk controller has a friend help
Spartan6_DDR2-
- Spartan6 硬核MCB读写DDR2 实战篇-Spartan6 real hard-core DDR2 MCB articles to read and write
IDEinterface
- IDE接口时序和最全的接口定义，通过它可以实现硬盘的扇区读写-IDE interface timing and the most comprehensive interface definition, it can be achieved by sector hard disk read and write
Verilog_UDP
- 辛辛苦苦找到的UDP的资料，在verilog中UDP指的是用户定义的原语。比如说大家有时候会见到“primitive...table...endtable...endendprimitive”这样的代码段，在书上只能找到大概的解释。到网上查的话又老是跟TCP/IP的UDP冲突。所以特地搜集到了这个东西，希望能帮助大家解决“用户原语”相关的问题。-UDP hard to find the information in verilog in the UDP refers to the user-de
state-machine-design
- 状态机设计的苦干个不错的例子，ＶＨＤＬ语言编写，相信会对verilog的学习者有帮助-State machine design a good example of hard work, VHDL language.Ｉthink it will help verilog learners
ViterbiDecodeK9R12HardDecision
- viterbi 硬判决译码，基本实现了（2，1，9）卷积码的硬判决译码，用modelsim RTL仿真通过-hard-decision viterbi decoding, the basic realization of the (2,1,9) convolutional codes hard decision decoding, using modelsim RTL simulation through
vhdl-Algorithm-Hard-wired-logic
- 大型数字系统设计中，vhdl中从算法到硬线逻辑实现的教程-Large-scale digital system design, vhdl from hard-wired logic algorithm to realize the Tutorial
Design-Space-Exploration-of-Hard-Decision-Viterbi
- Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation