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FrequencySpectrum
- 基于ep1c6q240c8 fpga 及msp430fg4618混合控制器的频谱分析仪控制代码-Based on ep1c6q240c8 fpga and msp430fg4618 Hybrid Controller spectrum analyzer control code
DSPHBControl
- DSP Example Code for programming an Hybrid AC/DC converter-DSP Example Code for programming an Hybrid AC/DC converter
NIOS_I2C_SD2405_AT24C128
- 基于NIOS的I2C总线，AT24C128和SD2405实时时钟芯片混合编程驱动。在I2C地址选择处有经典用法！-I2C-bus based NIOS, AT24C128, and SD2405 hybrid programming driven real time clock chip. I2C address selection in the Department has the classic usage!
mix
- 本代码是基于Verilog语言，是在伽罗瓦域GF(2^8)上完成加法和乘法运算，主要完成ASE加密的列混合运算-This code is based on the Verilog language, is the Galois field GF (2 ^ 8) on the completion of addition and multiplication, the main column of the completion of ASE encryption hybrid operation
conformPulse
- 本程序实现了对两相混合式电机提供4路驱动信号，相位相差90，180，另外也提供了拨码开关控制的频率输出选择，输出频率最大是5M,外部全局时钟是10M，采用的芯片是epm7128slc-84-15, 管脚分配可以参考管脚分配文件，对应驱动电机信号是两相双极性A+,A-,B+,B-. 编译环境是quartusII 8.0,这段代码可用来调试步进电机双桥驱动电路，也可用当信号发生器使用。-The program realization of two-phase hybrid motor provide
AHB
- 基于混合优先权算法的AHB总线仲裁器的设计-Hybrid algorithm based on priority AHB bus arbiter design
v3-1-4-12
- A Novel VLSI Architecture of Hybrid Image Compression Model based on Reversible Blockade Transform
Digital-Calculator
- 用汇编语言编写一个能实现四则混合运算、带括号功能的整数计算器程序。程序能实现键盘十进制运算表达式的输入和显示，按“=”后输出十进制表示的运算结果。-A four hybrid operation, with brackets function integer calculator program written in assembly language. Program to achieve keyboard decimal arithmetic expression input and out
reversible-squarer
- it is hybrid squarer circuit which will be designed using reversible gates which having les hardware complexity with compared to the conventional gates
4-2-compressor
- IT IS THE HYBRID COMPRESSOR WHICH WILL BE USEFUL LOW POWER SINCE THE GATE COUNT AND DELAY REQUIRED IS VERY LESS COMPARED TO THE NORMAL DESIGN
Pico_Lab3_Uart
- FPGA嵌入式编程,PicoBlaze实现方式。ISE和XPS混合方式-FPGA embedded programming, PicoBlaze implementation. ISE and XPS hybrid approach
20161227_sf
- AES加密算法中的列混合模块的FPGA实现源代码，采用Verillog语言，在软件Quartus II上综合-AES encryption algorithm in the FPGA column hybrid module implementation source code, using language Verillog integrated in the Quartus II software
step_motor
- 2相混合式步进电机驱动程序，配套MC860H驱动器，共阴极接法 EN提前DIR至少5us，正常工作为高电平 DIR提前PUL下降沿5us确定其状态高或底，DIR 高：正转，底：反转 PUL脉冲信号，高电平不小于2.5us，低电平不小于2.5us(2 phase hybrid stepper motor driver, matching MC860H driver, common cathode connection method.EN advance DIR at least 5us, n