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lab4
- vhdl uart lab ENTITY uart IS PORT ( SIGNAL clock,reset : IN STD_LOGIC SIGNAL sdatain : IN STD_LOGIC SIGNAL oready, sdataout : INOUT STD_LOGIC SIGNAL iready : INOUT STD_LOGIC SIGNAL charin : INOUT STD_L
vga_demo2
- VGA controller : Genarate a VGA signal from your inout information as color info of each pixel-VGA controller : Genarate a VGA signal from your inout information as color info of each pixel
cruels-inout
- 这是自己的原创，关于fpga的verilog代码中inout错误提示的理解-This is your own original, on the verilog fpga error code understanding inout
inout_test
- there are two madules,both of them contain an inout port,As module1 sends out data on its inout port,the inout port on second module would be an input,and vice versa
DMA
- DMA controller VHDL code entity dma is generic ( ADDR_WIDTH : integer := 16 -- default value DATA_WIDTH : integer := 16 -- default value ) port ( RESET_L : in std_logic CLK : in std_logic DRQ_L : in std_logic DMAA
inout-vhdl
- c p u 读inout 端口的vhdl 程序-Read inout port vhdl program
Verilog_inout_
- verilog语言中inout端口的使用方法介绍-verilog language inout ports using the method described
INOUT
- 一个实现特定功能的FPGA程序，使用VHDL语言编写，用于排除FPGA影响，检测电路中其他芯片是否正常工作-A function of the FPGA to achieve a specific program, the use of VHDL language for FPGA exclude the impact of other chip detection circuit is working properly
Verilog-language-in-ASIC-design
- Inout bidirectional port programming based on Verilog language in ASIC design
udp_send1
- 基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output
inout
- 用于RAM的测试文件，以及testbench-some RAM testingfiles，and its testbench
Adept SDKv1-3
- 开发板资料，适用于赛灵思的板子，欢迎大家下载(Examine your code to determine if this port should be declared as an INOUT, or if the assignment to this port should not have been made. If this signal connects to submodules, consider the type and lower-level functionality of