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wishbone_i2c_master
- -- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on simple_i2c -- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman) -- rev. 0.3 may 4th 200
HARDWARE-DESIGN-AND-IMPLEMENTATION-ISSUES-ON-A-FPG
- 这篇论文的中文名字是：基于FPGA的智能摄像机的设计和实现。对于将要开发智能摄像的工程师来说，这篇论文将提供很大的帮助。
uCLinux_on_NiosII.rar
- NIOS II平台下，uClinux的移植笔记，详细地记录了移植中需要注意的问题。,NIOS II platform, uClinux porting notes, a detailed record of the migration issues that need attention.
Verilog_UDP
- 辛辛苦苦找到的UDP的资料，在verilog中UDP指的是用户定义的原语。比如说大家有时候会见到“primitive...table...endtable...endendprimitive”这样的代码段，在书上只能找到大概的解释。到网上查的话又老是跟TCP/IP的UDP冲突。所以特地搜集到了这个东西，希望能帮助大家解决“用户原语”相关的问题。-UDP hard to find the information in verilog in the UDP refers to the user-de
logicassign
- 同一基类型的两分辨类型的赋值相容问题,各个源描述的编译顺序是:logic.vhd,assign.vhd-The same base type to distinguish the two types of assignment compatibility issues, the various sources described in the order of the compiler: logic.vhd, assign.vhd
FPGA-basedhardwareimplementationofneuralnetworks.r
- 基于FPGA的神经网络硬件实现中的关键问题研究，适合用fpga研究神经网络的工程人员参考-FPGA-based hardware implementation of neural networks in the study of key issues for research with neural networks fpga reference works
ebook_verilog_fine_state_machine
- Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
2
- FPGA设计中几个基本问题的分析及解决 多时钟系统，时钟设计，时钟歪斜，门控时钟，毛刺信号及其消除，FPGA中的延时设计，FPGA设计应注意的其它问题-FPGA design analysis of a few basic questions and solve multi-clock system, clock design, clock skew, clock gating, and the elimination of burr signal, FPGA design of the d
vhdl_design
- 介绍VHDL编程技巧，注意事项的好资料。适合接触过vhdl一段时间的人-Introduction VHDL programming skills, good attention to information issues. Vhdl for some time to come into contact with people
memtest
- 在数字系统中，一般存在多个芯片，利用不同的特点用于实现不同的功能，一般都包含CPU,FPGA,AD,DA,memory，ASSP（专用标准模块）,ASIC等。CPU用于进行智能控制，FPGA进行硬件算法处理和多设备接口，AD进行模数转换，DA进行数模转换，memory存储临时数据。因此，FPGA如何与其他芯片进行通讯是重要的设计内容。数据输入，数据输出，双向通讯，指令传递，地址管理，不同时钟的异步通讯问题等等都需要处理。最基本的MEMORY如SRAM(128KX8bbit静态存储器628128)
VHDLtraining
- The basic concepts of VHDL language 1.1 Data types and data objects declared 1.2 VHDL descr iption of the syntax 1.3 Class design 1.4 functions, procedures and packages 1.5 Issues and discussion 1.6 References-The basic concepts of VHDL l
KD-CPU
- 计算机原理课程设计给予Verilog做的课题，丰富的指令支持，LOOP，TRAP、以及子程序调用等-Principles of curriculum design to do the computer issues a rich instruction support, LOOP, TRAP, and subroutine calls, etc.
Design_of_Embedded_Control_Systems
- This volume presents new results in the design of embedded control systems, each chapter authored by an expert. The text focuses on current issues with new approaches for the analysis and synthesis of discrete systems and is aimed at programmable log
Digital_Signal_Integrity
- Book on PCB digital signal integrity issues.
practical_design_verification
- Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors explain both formal tec
key1
- 矩阵键盘实验1：向用户介绍矩阵键盘扫描实现的方法，没有考虑去抖和判断键弹起的问题；把相应的键值显示在数码管上-Matrix Keyboard Lab 1: Introduction to the user to achieve the keyboard scan matrix approach, not considered to shake and bounce to determine key issues the corresponding keys on the display in
FPGAclock
- FPGA设计中，时钟设计是很重要的一环，本文主要描述了FPGA设计中时钟设计的重要事项-FPGA design, clock design is a very important part, this paper describes the design of FPGA design, the clock on important issues
44317447-Vhdl-Sim-Syn
- This document is meant to be an introduction to VHDL both as a simulation language and an input language for automatic logic synthesis. It is based on material originally prepared for the ASIC Design Laboratory taught at the University of Twente
Verilog-example-135-
- 非常适用的Verilog程序，含有135个相关问题的Verilog程序代码，方便大家使用。-Verilog procedures are applicable, with 135 issues related to Verilog code, we facilitate use.
tft
- 好东西，重要的是分享，此压缩包文件是关于怎样使用tft液晶屏的，还有是关于fpga与dsp通信的实现，大家好好讨论讨论，相互提高-Good thing, it is important to share, if there are any questions, or what the key issues, we have a good discussion to discuss with each other to improve