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oc_mkjpeg
- Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.-Pure hardware JPEG Encoder design.
Mars_EP1C6F_Fundermental_demo(Verilog)
- FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and multiplier, such as MUX.
jpegVerilog
- FPGA实现jpeg Verilog源代码-FPGA realization of jpeg Verilog source code
MSP430C
- 用FPGA实现JPEG的Verilog源代码-JPEG with the FPGA implementation of the Verilog source code
jpeg
- 一个较小的JPEG解码程序，所有代码都在一个源文件中-A smaller JPEG decoding process, all the code in a source file
djpeg
- JPEG解码的Verilog源码，适合于了解JPEG的算法。-JPEG decoding of Verilog source code, for understanding the JPEG algorithm.
Jpeg_decoder
- It is jpeg_decoder program. Source code are C and Verilog HDL.File .c reads data from jpeg and convert it to binary bit stream.Decoder is by verilog file
jpegencode_latest.tar
- 完整的用VERILOG语言开发的图像压缩器代码，欢迎分享。-A jpeg encode source code based on verilog
mkjpeg.tar
- 用FPGA实现的JPEG编码器，可以直接使用，内含完成说明文档，经过验证无误。-• JPEG baseline encoding JPEG ITU-T T.81 | ISO/IEC 10918-1 • Standard JFIF header v 1.01 automatic generation • Color images only (3 components, RGB 24 or 16 bit, YUV input) • T
JPEG
- JPEG Encoder Verilog Source Code
jpegencode
- Verilog源码，实现jpeg图片的编解码,内附代码说明文档。-verilog source code to realize the encodeing and decodeing for JPEG