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jsq
- 本程序为24小时计时器，稳定无误差。简单好用，是Verilog HDL语言初学者的指引。-This procedure for 24-hour timer, stable error-free. Easy-to-use, is the Verilog HDL language beginners guide.
vhdl
- 抢答器里的基本原程序,抢答模块，计时器电路JSQ的VHDL源程序，译码器电路YMQ的VHDL源程序-VHDL
jsq
- 包括异步计数器，序列码发生器，两个程序都可以运行-Both programs can run asynchronous counters, serial number generator,
jsq
- 基于spartan—3E 开发板的一个PS/2键盘主机键盘的双键盘输入的带语音功能了计算器,通过VGA显示在电脑屏幕上,-Spartan-3E development board a PS/2 keyboard host keyboard keyboard with voice input function calculator via the VGA display on a computer screen,
jsq
- 基于FPGA的计算器，可以实现加减乘除运算功能，由于时间问题，浮点运算未能实现，其中的二进制与BCD码相互转换的模块可以使用-FPGA-based calculator, arithmetic calculation function can be achieved, due to time issues, floating-point operations failed to achieve, including binary and BCD code conversion modules t
jsq
- 一个在ise平台上写的计算机小程序，可以计算加减乘除，输入位数为10位，三位小数-A computer on the ise platform to write a small program, you can calculate the addition and subtraction multiplication and division, the input bit is 10, three decimal