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国外的VHDL应用例子
- 国外的VHDL应用例子，大家可一好好参考一下！-abroad VHDL Application examples, we can make reference to a properly!
sorce
- 一个很好的利用verilog编程实现的cpu程序，一定要好好利用。-a good use of the Verilog Programming cpu procedures, we must make good use of.
richic_vga_top
- 有关 VHDL进行VGA显示的源程序，请大家好好参考-VHDL for the VGA display the source code, please make reference to
fenpin(vhdl)
- 使用VHDL编写的分频程序,能进行任意次的偶数分频,程序简单易懂,供 初学者参考-prepared by the use of VHDL-frequency procedures can make even the random frequency, the procedures are simple and easy to understand. reference for beginners
VERILOGBLOCK
- 在blocking 模块中按如下写法，仿真与综合的结果会有什么样的变化？作出仿真 波形，分析综合结果。 -in blocking module by the following wording, simulation and synthesis of the results will be what kind of changes? Make simulation waveform analysis and comprehensive results.
uart_verilog
- 包含UART口的VERILOG源程序，该程序在FPGA上验证通过，可作为芯片设计，或FPGA设计的一个完整IP核，硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
shixian.rar
- 该文件是一份本人设计的实验报告，报告内详细说明了用VHDL语言，设计一个三位动态显示的计数器。采用模块化得设计，设计通过了仿真以及下载实现。总的文件是：shixian.vhd,下面包括四个元件：jishu1000.vhd,xzqh.vhd,senvedec.vhd,disp.vhd.,this paper uses vhdl to complement a design about how to make three leds display at the same time.
verilog1
- 用verilog语言编写的6分频分频计数器。分频后用来控制蜂鸣器响，也可以修改代码做成更高分频的计数器。压缩包内也包含此分频器的modelsim仿真文件-Verilog language with 6 frequency divider counter. Frequency and used to control the buzzer sound, you can modify the code to make a higher frequency counter. Compressed pac
pid_controler_latest.tar
- PID控制器的verilog实现，做闭环控制器的人可以参考-PID controller verilog implementation of closed-loop controller may make reference to
fsmled
- verilog语言, 状态机实现数码管显示 -This uses verilog language to make state machine realization of digital control
ex8_9_PLL
- FPGA入门，PLL不再是难题；本文件包提供PLL的的程序，供大家参考，请做出批评-FPGA Starter, PLL is no longer a problem this package provides procedures for the PLL, for your reference, please make a critical
sata_device_model
- sata_device_model,对做硬盘控制器的朋友有帮助-sata_device_model, to make the hard disk controller has a friend help
xilinxfpga_jtag
- XilinxUSB EEPROM是xilinx usb下载线的EEPROM程序，可以用来做xilinx的usb下载线-XilinxUSB EEPROM is xilinx usb download cable in the EEPROM program can be used to make the usb xilinx download cable
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
TEST5
- 这个是秒表的程序,很简单,不要取笑,多多交流了-This is a stopwatch procedures, is very simple, do not make fun of, a lot of exchange of
11
- VHDL语法的支持范围是不一样的，以下程序中的某些语句可能不能运行在所有的软件平台之上，因此程序可能要作一些修改，同时务必注意阅读程序中的注释。以下部分程序为txt格式，请自行另存为vdh后缀的文件。有些EDA软件要求ENTITY的名称和文件名要相同，也请自行修改。 如发现错误请来信指正或在BBS上提出。 -VHDL syntax support is not the same as the scope, the following procedures for some of the st
travel
- 自己做的vhdl课程设计，交通灯：实现主干道倒计时，分别为30,20,5秒，分情况：当主干道有车时，红黄绿交替，当只一个道路上有车时，那个道的交通灯变绿色，利用max+plus2做成，使用flex8000,epf8282alc84_4只用加一个38译码器模块即可，使用别的板子也可以运行-VHDL to do their own curriculum design, traffic lights: the realization of the trunk road countdown, 30,20
miniuart.tar
- Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication is very common that almost eve
I2C
- I2C core code in Hardware descrption language so as enable a cpld/fpga to be programmed for specific customized applications of our requirment & make the pcb work to meet the application requirements.
use-AUTHERWARE-to-make-LED-display
- 用AUTHERWARE制作体育馆大屏幕的方法与技巧-use AUTHERWARE software to make LED display