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  1. VHDL_DMF

    0下载:
  2. Vhdl实现扩频通信匹配滤波器,书上打下来的,打了好久.-VHDL realization of spread spectrum communication matched filter, books, playing down, playing for a long time.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:1.44kb
    • 提供者:刘小姐
  1. MatchFilter

    1下载:
  2. VHDL语言实现8路并行输入,8路并行输出,直接序列扩频接收机的高速匹配滤波。 -VHDL language to achieve 8-channel parallel input, 8-channel parallel output, high-speed direct-sequence spread spectrum matched filter receiver.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-24
    • 文件大小:7.62mb
    • 提供者:袁磊
  1. PN_code_capture_and_tracing

    0下载:
  2. 一个完整的pn码捕获与跟踪的VHDL源码,并行匹配滤波器捕获,锁相环跟踪.-A complete pn Code Acquisition and Tracking of the VHDL source code, parallel matched filter to capture, phase-locked loop tracking.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:2.05kb
    • 提供者:王永俊
  1. 2046matchedfilter

    0下载:
  2. 2046点匹配滤波器,附带C/A码生成模块一个-2046 points, matched filter, with C/A code generation module 1
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-06-16
    • 文件大小:23.98mb
    • 提供者:余彦培
  1. dmfilter

    0下载:
  2. gps接收机伪码捕获时采用的匹配滤波器,能完成接收码的捕获。-gps receiver pseudo-code used to capture the matched filter, receiving yards to complete the capture.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-04
    • 文件大小:1.11kb
    • 提供者:易凯
  1. LCD1602

    0下载:
  2. 基于FPGA EPM1270芯片设置的LCD1602液晶显示,已通过测试,显示完全正常,引脚已配好,下载直接使用-Based on the FPGA EPM1270 chip set LCD1602 liquid crystal display, has passed the test, showed completely normal, pins have been matched, downloaded directly use
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-09
    • 文件大小:94.43kb
    • 提供者:周涛
  1. dmf_vhdl

    0下载:
  2. digital Matched Filter design - including the clock synchronization of the design and its implementation-digital Matched Filter design - including the clock synchronization of the design and its implementation..
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-27
    • 文件大小:412.76kb
    • 提供者:kalyan
  1. pulse_exp

    0下载:
  2. 可配占空比、脉冲个数,受输入trigger的脉冲产生器(The pulse generator with input trigger can be matched with the null ratio and the number of pulses)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-21
    • 文件大小:1kb
    • 提供者:阿士大夫
  1. counter10

    0下载:
  2. vhdl编写的十进制计数器,名字叫count10,已配好引脚(VHDL's decimal counter, named count10, has been matched with a pin)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-01
    • 文件大小:1.36mb
    • 提供者:li 234
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