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LogicLock
- 实现数字混频，verilog与原理图混合编程-Digital mixer, verilog and mixed programming schematic
ip_digifrec
- The Digital IF Receiver megafunction combines a quadrature NCO and a digital mixer to translate the input IF signal down to baseband
Digital_mixer
- This fil eimplement a digital mixer by VHDl and contains a test bench too.
ddc_easy
- 简单的DDC实现，包括了DDS MIXER 等部分采用的VHDL语言-The implementation of DDC using vhdl hardware descr iption language
Multiplieur-signe
- VHDL code of a signed mixer with a testbench !
E2_4_SimSigPrduce
- 混频器 利用FPGA实现625khz乘以625khz混频器的设计-mixer come ture 625khz*625khz
dds_mixer
- 包括dds的产生 已经混频 里面包括详细的仿真 以及matlab验证-dds mixer matlab vhdl
fpgaUPDW
- fpga上下变频混频实现，其中CIC采用多种方法设计，自己花两个星期编写，中文注释，浅显易懂-fpga up and down conversion mixer implemented which CIC using a variety of methods designed, he spent two weeks writing notes in Chinese, easy to understand
DDC_FPGA
- 基于FPGA的数字下变频器（DDC）的设计,将采样得到的高速率信号变成低速率基带信号，以便进行下一步的信号处理。由NCO、数字混频器、低通滤波器和抽取滤波器四个模块组成。采用自编的加法树乘法器，提高乘法运算效率。-Design based on FPGA digital downconverter (DDC), the high-speed signal will be sampled baseband signal into a low rate for the next step in th
hunpin
- 数字电路任意频率混频器用FPGA来实现完成-FPGA Implementation of digital mixer
mixer_tx
- Digital Mixer: 16-bit signed input with DDS