uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB

本工程用来配置Altea 系列FPGA芯片管教，可以配置stratix II 系列芯片。-This design allows for configuration from multiple pages with either the Stratix PGM pins (remote/local) or the Dipswitch (MPGM pins)as the page select source(non-remote/local). It can configure stratix II

8 BIT BOOTH MULTIPLIER

package for image reading and writing in vhdl