搜索资源列表
pulse_change
- 用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS--use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-
Game_HLD3
- 基于fpga和xinlinx ise的小游戏的vhdl程序，希望对你有所帮助！-xinlinx and they simply based on the small game and ideally the VHDL process, and I hope to help you!
Max232ForHLD3(20040913)(OK)
- 基于fpga和xinlinx ise的串行通信vhdl程序，希望对你有所帮助！-xinlinx and ideally serial communications VHDL process, and I hope to help you!
Music_HLD3
- 基于fpga和xinlinx ise的音乐播放器vhdl程序，希望对你有所帮助！-and xinlinx ideally music player VHDL process, and I hope to help you!
dianzizhong
- 这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!-This is my learning process in the middle of the 10-minute program, containing various clock module and the counter, accumulator, and can download, compile!
一些VHDL源代码
- 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
430VS串口
- 给予MSP430F147的串口通讯程序,能帮助你了解MSP430系列单片机和串口通讯的基本方法-give MSP430F147 Serial communication process can help you understand the MSP430 MCU serial communications and the basic methods
CH1VHDL 数字电路参考书所有程序1
- VHDL 与数字电路设计程序参考书所有程序 1-VHDL and digital circuit design process all the procedures a reference book
baud
- vhdl 很好用于串行通信. 三个模快,发生时钟,发送和 接收过程-VHDL good for serial communication. Three die fast, occurred clock, sending and receiving process
Visio-绘图21
- 这是asic流程例子.文件内容已经验证过.如有疑问和我联系-This is the process blends example. The contents of the documents has been proven. And I doubt if links
44vhdl
- 44个vhdl实例 注1： 含有不可综合语句，请自行修改 注2： 一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意 注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化-44 VHDL examples Note 1 : Includes an integrated statement, the initiative to revise Note 2 : Some PLD only allows I / O exte
fpga-example2
- ASK调制与解调VHDL程序及仿真 FSK调制与解调VHDL程序及仿真 PSK调制与解调VHDL程序及仿真 基带码发生器程序设计与仿真 频率计程序设计与仿真-ASK modulation and demodulation VHDL simulation procedures and FSK modulation and demodulation process and VHDL simulation PSK modulation and demodulation process
pwm-20010309[1].tar
- PWM产生程序，绝对经典，好就顶一下先，谢谢了-PWM a process absolute classics, and what good on top first, I thank the
EDAchuzuchejijia
- 在本示例程序中，用VHDL语言实现了出租车的记价功能，在Maxplus2环境下编写，可通过cpld下载板来验证程序。在压缩包中附有示例的目的，方法和仿真时序图，是学习VHDL好例子。-in this sample program, using VHDL of the entry price of a taxi function, in preparation FLEX10K environment, through cpld download plate to the verification
FPGAdesignstudy
- 介绍了FPGA设计全流程 和一些简单的例子-introduced FPGA design the whole process and some simple examples
duble-process-lock
- 编写由两个主控进程构成的与上述功能相同的符号化Moore型有限状态机-The process of writing composed by two main control functions with the same symbol of Moore-type finite state machine
Huawei-FPGA-design-process-guide
- Huawei FPGA design process guide.
Process-P-FPGA_1
- this document contain many search papers wich descrid the system Process trainer PT326 and the control method of systems using FPGA
Process-control-module-VHDL-code
- 此为基于FPGA的直流伺服系统的设计，具体为过程控制模块VHDL代码-This is the dc servo system based on FPGA design, specific for process control module VHDL code
FPGA-QUARTUS_II-process
- 使用QUARTUS_II做FPGA开发全流程 程序-FPGA development QUARTUS_II do the whole process procedures