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user_logic_Open_I2C
- iic implementation,用verilog实现了IIC标准协议的功能-iic implementation, verilog achieved using standard protocols IIC function
Booth_4
- 用VERILOG 编写的弹球游戏，其中涉及到VGA协议和接口开发设计-Written with the VERILOG pinball game, which involves the development and design VGA protocols and interfaces
LAOWAI
- 一个老外写的HDLC协议，包括说明文件，很有参考价值-Written by a foreigner HDLC protocols, including documentation, of great reference value
Chapter-6
- 用Verilog编写的SPI协议包括了最基本的协议和功能，并通过测试。本SPI是主。-SPI using Verilog written agreement includes the most basic protocols and functions, and passing a test. The SPI is the main.
zorro_to_wishbone_bridge_latest.tar
- This project intends to create a bridge between Wishbone and the Amiga Zorro II and Zorro III busses. As in the Amiga 3000/4000 computer families, it is intended to support both the Zorro II and Zorro III protocols at the same time on the same bus.
msp430_FPGAcommunicatecode
- 本代码是通过msp430f149与fpga实现的两者通信程序，包含自己设定的协议-This code is msp430f149 fpga implementation of both communication and procedures, contains its own set of protocols ..
verilogiic1121
- 用HDL语言实现的I2C核,I2C在串行协议中,属于较复杂的协议,本程序使用方便,可以直接加到你的设计中.-HDL language with the I2C core, I2C serial protocol in, belong to the more complex protocols, the program easy to use, can be directly added to your design.
sgmii_latest.tar
- This core implements Physical Coding Sublayer of 1000BaseX transmission (IEEE 802.3 Clause36 and 37). This core can also be used for SGMII interface as this interface leverages 1000BaseX PCS. The differences between the 2 protocols are Link-timer and
MYPCI
- PCI VHDL程序，根据PCI通信协议编写的，，，没有用IP核，。。。本人接触PCI不久，次代码可能会存在些问题，请各位高手指点指点，小弟不尽感激-PCI VHDL procedures, according to the PCI communication protocols written, without using IP cores. . . I contact PCI soon, there may be some minor code issues, please master g
sgmii_latest[1].tar
- 这个工程应用于千兆网传输的物理代码子层，同时也用于SGMII接口。两者不同之处是自动协商时链接定时器和控制信息。-This core implements Physical Coding Sublayer of 1000BaseX transmission (IEEE 802.3 Clause36 and 37). This core can also be used for SGMII interface as this interface leverages 1000BaseX PCS.
nocem
- 基于VHDL硬件描述语言，实现了一款硬件片上网络模拟器，对网络接口桥的实现也有所介绍。-NoCem is an integrated emulation environment for Network on a Chip research. Network on Chips are used for processing elements on a single die to communate over a packet switched network. This is in contr
rio_latest.tar
- rapidIO 的VHDL代码，包括协议和交换代码，非常棒，值得学习-rapidIO VHDL code, including protocols and exchange code, great, worth learning
wishbone
- Wishbone规范具有如下特点:简单、紧凑，需要很少的逻辑门 完整的普通数据据传输总线协议，包括单个读写、快传输、读一修改一写周期、事件周期 数据总线宽度可以是8-64位 支持大端(big-endian)和小端(litle-endian)，接口自动完成两者之间的转换。支持存储器映射、FIFO存储器、交叉互联 握手协议，允许速率控制 可以达到每个时钟周期进行一次数据传输 支持普通周期结束、重试结束、错误结束等总线周期形式 支持用户自定义的标志:采用MASTER/SLAVE体系结构 支持多点进程(
RS9600
- 这是用FPGA实现的RS232通信接口程序，波特率为9600，由于RS232的波特率是有容差的，因此该对时序做了专门的优化，以确保接收到正确的数据，（因为用FPGA做接口和协议是大材小用了，而且比较麻烦）-This is achieved using FPGA RS232 communication interface program, 9600, due to the RS232 baud rate is tolerance, so the timing made specifically o
uart_io_test
- verilog中UART的PC通信协议,看过的人都说好，已经验证正确性，很不错的代码。-verilog in the PC UART communication protocols, seen people say well, has verified the accuracy, very good code.
AHB_UVC_and_AHB_IC_Verificat
- ahb uvc is an on chip communication protocol for high speed integration and low power utilities performance protocols widely used in all vip applications
rs422_r
- 此功能模块实现了422标准协议的单字节接收功能，采用了起始位＋8位数据位+奇校验+1停止位的方式，实现了串行输入并行输出的功能。-This function module implements the standard protocols 422 single-byte receive function, using the start bit+ 8 data bits odd parity+1+ stop bits, enabling a serial input parallel outpu
rs422_t
- 此功能模块实现了422标准协议的单字节发送功能，采用了起始位＋8位数据位+奇校验+1停止位的方式，实现了并行输入串行输出的功能。-This function module implements the standard protocols 422 single-byte transmit function, the start bit+ 8 data bits odd parity+1+ stop bits, enabling a parallel input serial output.
learn2
- verilog i2c通讯协议，包括工程文件，可以直接打开-verilog i2c communication protocols, including the project file, you can directly open
Demultiplexing-200-MHz-Data-Streams
- Modern serial data protocols (e.g., FireWire, SONET, ATM, T4) sometimes require clocks that are faster than maximum FPGA global clock speeds. To solve this problem, the incoming clock (200 MHz in the example below) can be used to demultiple