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txxclock
- VHDL编写的数字钟，在Q-ii下编译，实现闹铃设置与定时闹铃，分时秒显示
数据结构c描述习题集答案
- 减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制位数）。 二、设计原理 输入/输出说明： d：异步置数数据输入； q：当前计数器数据输出； clock：时钟脉冲； count_en：计数器计数使能控制（1：计数/0：停止计数）； updown：计数器进行自加/自减运算控制（1：自加/0：自减）； load_d-a counter a reduction, design requirem
trunk-hdlc.rar
- 高级链路层协议的实现，vhdl，fpga,- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern
GFmultiply
- Verilog hdl语言 伽罗华域GF（q）乘法器设计，可使用modelsim进行仿真-Language Verilog hdl Galois field GF (q) multiplier design, can use the ModelSim simulation
SR_Latch
- RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit i
Galois_field_multiplier_verilog_design
- 伽罗华域GF（q）乘法器verilog设计.rar-Galois field GF (q) multiplier verilog design.rar
4multiplier
- 4位乘法器vhdl程序-- DEscr iptION : Signed mulitplier:-- A (A) input width : 4-- B (B) input width : 4-- Q (data_out) output width : 7-4 multiplier vhdl procedure
vmachine
- Verilog code for vending machine.. Descr iption: Vending machine ll take two quarters and distribute one of the two flavors of juice(apple or orange). Inputs: • Q : A quarter has been inserted. • O : orange juice button is press
Q
- 制作一个锁存器,常用于地址的所存,上升沿触发-DtoQ
GAFF
- 伽罗华域GF（q）乘法器设计,完整的源代码。-Galois field GF (q) multiplier design, the complete source code.
d-flip
- 同步复位的D 触发器，该触发器有一个数据输入端D，时钟输入端CLK，清 零输入端CLR，数据输出端Q。CLR为1时，触发器复位-Synchronous reset D flip-flop, the flip-flop has a data input D, the clock input CLK, clear input CLR, the data output Q. CLR 1, the trigger reset
4
- 双四选一数据选择器74LS153,1、写一个程序，用顺序描述语句和并发描述语句（选择信号代入语句或者条件信号代入语句）分别控制74LS153的一个输出端Q。 2、比较一下顺序语句与并行语句各自的优缺点。 输入：逻辑开关。输出：LED灯。 -A double four election data selector 74LS153, 1, write a program, with sequential and concurrent statements describe the sta
FPGA_design_summary_FAQ
- FPGA设计常见问题汇总:主要是fpga中经常会遇到一些问题的答疑，初学者必备手册-FAQ FPGA design summary: fpga main problems encountered frequently in the Q, beginners must have manual
dff
- 用VHDL语言编写的带进位、置位、复位的D触发器，异步清零D触发器，同步清零D触发器-library ieee use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all entity exp7_10 is port( clk: in std_logic d: in std_logic clr: in std_logic en,s:in std_logic q: o
ImplementationofHighSpeedUpDownConversionFIRFilter
- 为了对FPGA 的资源占用量最小，以便实现 片上系统(SoC)设计，充分利用了上下变频过程中I，Q 数据流的特点，仅用一套滤波器运算单元分时复用对I，Q 滤波，同时详细研究了滤波器的转置结构和位平面结构对FPGA资源占用量的差别。-Benefiting from the characteristics of I and Q data streams in the converter。 one set of computation units is multiplexed to fil
div_clk_01
- Simple D flip flip with D, clock, and Q.
ofdmbaseband
- the OFDM PHY is adaptive therefore it supports multiple schemes BPSK, QPSK, 16-QAM and 64-QAM for data carriers’ modulation. The constellation diagrams are gray mapped and shows the magnitudes I and Q (In-phase and Quadrature) components of e
keeloq encoder
- this code is a keeloq encryption verilog code-keeloq encryption verilog code
q
- tlc5510接口电路仿真程序，主要是在quaturs2软件中运行-The Technique of The Connection between The TLC5510 8-bit High-Speed
GF-(q)-multiplier-design
- 伽罗华域GF（q）乘法器设计,FPGA实现-Galois field GF (q) multiplier design, FPGA realization