搜索资源列表
CapacityRAMModel
- Capacity RAM Model的VHDL的例子。最佳的资源优化版。-Capacity Model RAM VHDL example. The best resource optimization version.
VHDL-ram_fifo
- VHDL的ram和fifo model code 包含众多的厂家
AMBA-Bus_Verilog_Model
- 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_R
ram
- 基于altera ep2c8双口RAM -Altera ep2c8-based dual-port RAM
ram_latest
- VHDL实现CISC模型微处理器设计（含有rom和ram）本程序实现的是输入10个数，输出最小负数-VHDL model to achieve CISC microprocessor design (with rom and ram) to achieve this procedure is the number of input 10 and output the smallest negative
VeriRISC_CPU_Verilog
- Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clo
SDRAMping-pong-memory-structure
- 双口RAM 的乒乓存储结构（芯片型号CY7C09279） 应用场合为FPGA向双口RAM不断写入数据，PCI总线从RAM读取数据。[已调试验证]-Dual-port RAM, ping-pong memory structure (chip model CY7C09279) applications for the FPGA to the dual-port RAM write data continuously, PCI bus read data from RAM. [Debugging
pudn
- Encoders, decoders and RAM Model
vhdl_ram
- Fast generic RAM model